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| author | Priyanka Jain <Priyanka.Jain@freescale.com> | 2015-06-05 15:29:02 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-07-28 14:40:57 -0700 |
| commit | 4b6067ae9ddd2113df18735e4f10d8d40fcb1c1e (patch) | |
| tree | 665cb5e0194930ffe336fec849644c5f9d64ebfb /board/freescale/t104xrdb/ddr.c | |
| parent | 26473945ad6667183296e7edee2a65edf31bb6f7 (diff) | |
| download | blackbird-obmc-uboot-4b6067ae9ddd2113df18735e4f10d8d40fcb1c1e.tar.gz blackbird-obmc-uboot-4b6067ae9ddd2113df18735e4f10d8d40fcb1c1e.zip | |
powerpc/T104xD4RDB: Add T104xD4RDB boards support
T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
T1040D4RDB is re-designed T1040RDB board with following changes :
- Support of DDR4 memory
- Support of 0x66 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
- Support of QE-TDM
Similarily T1042D4RDB is a Freescale reference board that hosts the T1040
SoC. T1042D4RDB is re-designed T1042RDB board with following changes :
- Support of DDR4 memory
- Support for 0x86 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
- Support of DIU
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/t104xrdb/ddr.c')
| -rw-r--r-- | board/freescale/t104xrdb/ddr.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index e1148e568e..cf79d2ddb2 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -75,7 +75,11 @@ found: * Factors to consider for half-strength driver enable: * - number of DIMMs installed */ +#ifdef CONFIG_SYS_FSL_DDR4 + popts->half_strength_driver_enable = 1; +#else popts->half_strength_driver_enable = 0; +#endif /* * Write leveling override */ @@ -91,8 +95,14 @@ found: popts->zq_en = 1; /* DHC_EN =1, ODT = 75 Ohm */ +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif } #if defined(CONFIG_DEEP_SLEEP) |
