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| author | Wolfgang Denk <wd@denx.de> | 2012-08-09 21:04:05 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2012-08-09 21:04:05 +0200 |
| commit | 1d56f63dab2d9b1ea60601f5f3ae22d8664d8aa5 (patch) | |
| tree | 249c74a50e495c32d6b8f387112f712430e38d22 /board/freescale/p2041rdb | |
| parent | d764c5043d6d72e012f3e50092344ebd57a0c242 (diff) | |
| parent | 5c5befda58e4a3f198a033e8a9952b2b309acc86 (diff) | |
| download | blackbird-obmc-uboot-1d56f63dab2d9b1ea60601f5f3ae22d8664d8aa5.tar.gz blackbird-obmc-uboot-1d56f63dab2d9b1ea60601f5f3ae22d8664d8aa5.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
powerpc/85xx: use CONFIG_SYS_FSL_PCIE_COMPAT macro when setting the PCI LIODNs
powerpc/mpc85xx: Ignore E bit for BSC9130/1
powerpc/sgmii: To support PHY link state auto detect in SGMII mode
powerpc/85xx: improve definition of BR_PHYS_ADDR macro
powerpc/p2041: configure the CPLD lane_mux according to RCW
powerpc/ddr: fix fsl_ddr_get_dimm_params compile error
powerpc/corenet: fix compile error when CONFIG_SYS_NO_FLASH is defined
powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134 for DDR over 4GB
powerpc/p1022ds: fix DIU/LBC switching with NAND enabled
powerpc/p1022ds: add support for SPI and SD boot
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'board/freescale/p2041rdb')
| -rw-r--r-- | board/freescale/p2041rdb/eth.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c index 4b0d577e2c..fec97773ea 100644 --- a/board/freescale/p2041rdb/eth.c +++ b/board/freescale/p2041rdb/eth.c @@ -136,6 +136,11 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, } #endif /* #ifdef CONFIG_FMAN_ENET */ +#define CPLD_LANE_A_SEL 0x1 +#define CPLD_LANE_G_SEL 0x2 +#define CPLD_LANE_C_SEL 0x4 +#define CPLD_LANE_D_SEL 0x8 + int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET @@ -143,6 +148,10 @@ int board_eth_init(bd_t *bis) struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; int lane; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + int srds_prtcl = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + u8 mux = CPLD_READ(serdes_mux); printf("Initializing Fman\n"); @@ -172,6 +181,36 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); + mux &= ~(CPLD_LANE_A_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL); + switch (srds_prtcl) { + case 0x2: + case 0xf: + mux &= ~CPLD_LANE_G_SEL; + break; + case 0x5: + case 0x9: + case 0xa: + case 0x17: + mux |= CPLD_LANE_G_SEL; + break; + case 0x14: + mux = (mux & (~CPLD_LANE_G_SEL)) | CPLD_LANE_A_SEL; + break; + case 0x8: + case 0x16: + case 0x19: + case 0x1a: + mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; + break; + case 0x1c: + mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL; + break; + default: + printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl); + break; + } + CPLD_WRITE(serdes_mux, mux); + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; |
