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authorYork Sun <yorksun@freescale.com>2013-09-30 09:22:09 -0700
committerYork Sun <yorksun@freescale.com>2013-11-25 11:43:43 -0800
commit5614e71b4956c579cd4419b958b33fa6316eaa92 (patch)
treef75d1d531814dbbe0ff9d65f28cc050a73a8f7de /board/freescale/p2020ds
parentac6880782d8f369b7121488e8407ae6ddcf2b9ff (diff)
downloadblackbird-obmc-uboot-5614e71b4956c579cd4419b958b33fa6316eaa92.tar.gz
blackbird-obmc-uboot-5614e71b4956c579cd4419b958b33fa6316eaa92.zip
Driver/DDR: Moving Freescale DDR driver to a common driver
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/p2020ds')
-rw-r--r--board/freescale/p2020ds/ddr.c6
-rw-r--r--board/freescale/p2020ds/p2020ds.c4
2 files changed, 5 insertions, 5 deletions
diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c
index b12141f296..debe70b18b 100644
--- a/board/freescale/p2020ds/ddr.c
+++ b/board/freescale/p2020ds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
@@ -37,7 +37,7 @@ static const struct board_specific_parameters dimm0[] = {
* num| hi| clk| cpo|wrdata|2T
* ranks| mhz|adjst| | delay|
*/
-#ifdef CONFIG_FSL_DDR2
+#ifdef CONFIG_SYS_FSL_DDR2
{2, 549, 4, 0x1f, 2, 0},
{2, 680, 4, 0x1f, 3, 0},
{2, 850, 4, 0x1f, 4, 0},
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index 58a42231a9..dd8c6b10fb 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <miiphy.h>
@@ -68,7 +68,7 @@ int checkboard(void)
phys_size_t fixed_sdram(void)
{
- volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
uint d_init;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
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