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authorTimur Tabi <timur@freescale.com>2010-07-21 16:56:19 -0500
committerKumar Gala <galak@kernel.crashing.org>2010-10-07 09:49:47 -0500
commita2d12f88129a0a1a7c18630b7a48ade22a48416e (patch)
treeacda8b16207894aabd2627f05119500eeee88c8c /board/freescale/p1022ds
parentb6bde930901b1375264865b979507eb25806cb77 (diff)
downloadblackbird-obmc-uboot-a2d12f88129a0a1a7c18630b7a48ade22a48416e.tar.gz
blackbird-obmc-uboot-a2d12f88129a0a1a7c18630b7a48ade22a48416e.zip
p1022ds: add audclk hwconfig setting to enable codec reference clock
The Freescale P1022DS can use either a 12.288MHz or a 11.2896MHz reference clock for the audio codec, but by default both are disabled. Add a 'audclk' hwconfig option that allows the user to choose which clock he wants. The 12.288MHz clock allows the codec to use sampling rates of 16, 24, 32, 48, 64, and 96KHz. The 11.2896 clock allows 14700, 22050, 29400, 44100, 58800, and 88200Hz. Also configure a pin muxing to select some SSI signals, which will disable I2C1. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale/p1022ds')
-rw-r--r--board/freescale/p1022ds/p1022ds.c67
1 files changed, 58 insertions, 9 deletions
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index 5cdee9ff70..ee93e8b815 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -27,6 +27,7 @@
#include <asm/mp.h>
#include <netdev.h>
#include <i2c.h>
+#include <hwconfig.h>
#include "../common/ngpixis.h"
@@ -90,34 +91,58 @@ phys_size_t initdram(int board_type)
#define CONFIG_TFP410_I2C_ADDR 0x38
+/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
+#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03
+
+/* Route the I2C1 pins to the SSI port instead. */
+#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08
+
+/* Choose the 12.288Mhz codec reference clock */
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02
+
+/* Choose the 11.2896Mhz codec reference clock */
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
+
int misc_init_r(void)
{
u8 temp;
+ const char *audclk;
+ size_t arglen;
- /* Enable the TFP410 Encoder */
+ /* For DVI, enable the TFP410 Encoder. */
temp = 0xBF;
if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
return -1;
-
- /* Verify if enabled */
- temp = 0;
if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
return -1;
-
debug("DVI Encoder Read: 0x%02x\n", temp);
temp = 0x10;
if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
return -1;
-
- /* Verify if enabled */
- temp = 0;
if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
return -1;
-
debug("DVI Encoder Read: 0x%02x\n",temp);
+ /*
+ * Enable the reference clock for the WM8776 codec, and route the MUX
+ * pins for SSI. The default is the 12.288 MHz clock
+ */
+
+ temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
+ CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
+ temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
+
+ audclk = hwconfig_arg("audclk", &arglen);
+ /* Check the first two chars only */
+ if (audclk && (strncmp(audclk, "11", 2) == 0))
+ temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
+ else
+ temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
+ out_8(&pixis->brdcfg1, temp);
+
return 0;
}
@@ -310,6 +335,27 @@ int board_eth_init(bd_t *bis)
}
#ifdef CONFIG_OF_BOARD_SETUP
+/**
+ * ft_codec_setup - fix up the clock-frequency property of the codec node
+ *
+ * Update the clock-frequency property based on the value of the 'audclk'
+ * hwconfig option. If audclk is not specified, then default to 12.288MHz.
+ */
+static void ft_codec_setup(void *blob, const char *compatible)
+{
+ const char *audclk;
+ size_t arglen;
+ u32 freq;
+
+ audclk = hwconfig_arg("audclk", &arglen);
+ if (audclk && (strncmp(audclk, "11", 2) == 0))
+ freq = 11289600;
+ else
+ freq = 12288000;
+
+ do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1);
+}
+
void ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
@@ -327,6 +373,9 @@ void ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif
+
+ /* Update the WM8776 node's clock frequency property */
+ ft_codec_setup(blob, "wlf,wm8776");
}
#endif
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