Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/p3060: Add SoC related support for P3060 platform
  powerpc/85xx: Add support for setting up RAID engine liodns on P5020
  powerpc/85xx: Refactor some defines out of corenet_ds.h
  fm-eth: Add ability for board code to disable a port
  powerpc/mpc8548: Add workaround for erratum NMG_LBC103
  powerpc/mpc8548: Add workaround for erratum NMG_DDR120
  powerpc/mpc85xxcds: Fix PCI speed
  powerpc/mpc8548cds: Fix booting message
  powerpc/p4080: Add support for secure boot flow
  powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASH
  powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boards
  powerpc/p2041rdb: remove watch dog related codes
  powerpc/p2041rdb: updated description of cpld command
  powerpc/p2041rdb: add more ddr frequencies support
  powerpc/p2041rdb: set sysclk according to status of physical switch SW1
  powerpc/p2041rdb: update cpld reset command according to CPLD 2.0
  powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver
  powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver
  powerpc/mpc8xxx: Add DDR2 to unified DDR driver
  powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps()
  powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots
  powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en
  powerpc/85xx: Refactor P2041RDB to use common p_corenet files
  powerpc/85xx: refactor common P-Series CoreNet files for FSL boards
  powerpc/85xx: Enable CMD_REGINFO on corenet boards
  powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries
  powerpc/85xx: Fix USB protocol definitions for P1020RDB
  powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM
  powerpc/mpc8xxx: Move DDR RCW overriding to common code
  powerpc/mpc8xxx: Extend CWL table
  powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536
  powerpc/85xx: Cleanup extern in corenet_ds board code
  powerpc/p2041rdb: Add ethernet support on P2041RDB board
  powerpc/85xx: Add networking support to P1023RDS
  powerpc/hydra: Add ethernet support on P5020/P3041 DS boards
  powerpc/85xx: Add FMan ethernet support to P4080DS
  powerpc/85xx: Add support for FMan ethernet in Independent mode
  powerpc/mpc8548cds: Cleanup mpc8548cds.c
  powerpc/mp: add support for discontiguous cores
  powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries
  fdt: Add new fdt_create_phandle helper
  fdt: Rename fdt_create_phandle to fdt_set_phandle
  powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set
  fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)
  powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)
  fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)
  powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M
  powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB
  nand: Freescale Integrated Flash Controller NAND support
  powerpc/85xx: Add basic support for P1010RDB
  powerpc/85xx: Add support for new P102x/P2020 RDB style boards
  powerpc/85xx: relocate CCSR before creating the initial RAM area
  powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros
  powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0
  powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014

1 files changed, 84 insertions, 33 deletions

diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index b93701571b..3b4dfa3f8c 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -118,53 +118,111 @@ typedef struct {
 	u32 force_2T;
 } board_specific_parameters_t;
 
-/* ranges for parameters:
- *  wr_data_delay = 0-6
- *  clk adjust = 0-8
- *  cpo 2-0x1E (30)
- */
-
-
-/* XXX: these values need to be checked for all interleaving modes.  */
-/* XXX: No reliable dual-rank 800 MHz setting has been found.  It may
- *      seem reliable, but errors will appear when memory intensive
- *      program is run. */
-/* XXX: Single rank at 800 MHz is OK.  */
-const board_specific_parameters_t board_specific_parameters[][30] = {
+const board_specific_parameters_t board_specific_parameters_udimm[][30] = {
 	{
 	/*
 	 * memory controller 0
 	 *  lo|  hi|  num|  clk| wrlvl | cpo  |wrdata|2T
-	 * mhz| mhz|ranks|adjst| start | delay|
+	 * mhz| mhz|ranks|adjst| start |      |delay |
 	 */
 		{  0, 850,    4,    4,     6,   0xff,    2,  0},
 		{851, 950,    4,    5,     7,   0xff,    2,  0},
 		{951, 1050,   4,    5,     8,   0xff,    2,  0},
 		{1051, 1250,  4,    5,    10,   0xff,    2,  0},
 		{1251, 1350,  4,    5,    11,   0xff,    2,  0},
+		{1351, 1666,  4,    5,    12,   0xff,    2,  0},
 		{  0, 850,    2,    5,     6,   0xff,    2,  0},
 		{851, 950,    2,    5,     7,   0xff,    2,  0},
 		{951, 1050,   2,    5,     7,   0xff,    2,  0},
 		{1051, 1250,  2,    4,     6,   0xff,    2,  0},
 		{1251, 1350,  2,    5,     7,   0xff,    2,  0},
+		{1351, 1666,  2,    5,     8,   0xff,    2,  0},
+		{  0, 850,    1,    4,     5,   0xff,    2,  0},
+		{851, 950,    1,    4,     7,   0xff,    2,  0},
+		{951, 1050,   1,    4,     8,   0xff,    2,  0},
+		{1051, 1250,  1,    4,     8,   0xff,    2,  0},
+		{1251, 1350,  1,    4,     8,   0xff,    2,  0},
+		{1351, 1666,  1,    4,     8,   0xff,    2,  0},
 	},
 
 	{
 	/*
 	 * memory controller 1
 	 *  lo|  hi|  num|  clk| wrlvl | cpo  |wrdata|2T
-	 * mhz| mhz|ranks|adjst| start | delay|
+	 * mhz| mhz|ranks|adjst| start |      |delay |
 	 */
 		{  0, 850,    4,    4,     6,   0xff,    2,  0},
 		{851, 950,    4,    5,     7,   0xff,    2,  0},
 		{951, 1050,   4,    5,     8,   0xff,    2,  0},
 		{1051, 1250,  4,    5,    10,   0xff,    2,  0},
 		{1251, 1350,  4,    5,    11,   0xff,    2,  0},
+		{1351, 1666,  4,    5,    12,   0xff,    2,  0},
 		{  0, 850,    2,    5,     6,   0xff,    2,  0},
 		{851, 950,    2,    5,     7,   0xff,    2,  0},
 		{951, 1050,   2,    5,     7,   0xff,    2,  0},
 		{1051, 1250,  2,    4,     6,   0xff,    2,  0},
 		{1251, 1350,  2,    5,     7,   0xff,    2,  0},
+		{1351, 1666,  2,    5,     8,   0xff,    2,  0},
+		{  0, 850,    1,    4,     5,   0xff,    2,  0},
+		{851, 950,    1,    4,     7,   0xff,    2,  0},
+		{951, 1050,   1,    4,     8,   0xff,    2,  0},
+		{1051, 1250,  1,    4,     8,   0xff,    2,  0},
+		{1251, 1350,  1,    4,     8,   0xff,    2,  0},
+		{1351, 1666,  1,    4,     8,   0xff,    2,  0},
+	}
+};
+
+const board_specific_parameters_t board_specific_parameters_rdimm[][30] = {
+	{
+	/*
+	 * memory controller 0
+	 *  lo|  hi|  num|  clk| wrlvl | cpo  |wrdata|2T
+	 * mhz| mhz|ranks|adjst| start |      |delay |
+	 */
+		{  0, 850,    4,    4,     6,   0xff,    2,  0},
+		{851, 950,    4,    5,     7,   0xff,    2,  0},
+		{951, 1050,   4,    5,     8,   0xff,    2,  0},
+		{1051, 1250,  4,    5,    10,   0xff,    2,  0},
+		{1251, 1350,  4,    5,    11,   0xff,    2,  0},
+		{1351, 1666,  4,    5,    12,   0xff,    2,  0},
+		{  0, 850,    2,    4,     6,   0xff,    2,  0},
+		{851, 950,    2,    4,     7,   0xff,    2,  0},
+		{951, 1050,   2,    4,     7,   0xff,    2,  0},
+		{1051, 1250,  2,    4,     8,   0xff,    2,  0},
+		{1251, 1350,  2,    4,     8,   0xff,    2,  0},
+		{1351, 1666,  2,    4,     8,   0xff,    2,  0},
+		{  0, 850,    1,    4,     5,   0xff,    2,  0},
+		{851, 950,    1,    4,     7,   0xff,    2,  0},
+		{951, 1050,   1,    4,     8,   0xff,    2,  0},
+		{1051, 1250,  1,    4,     8,   0xff,    2,  0},
+		{1251, 1350,  1,    4,     8,   0xff,    2,  0},
+		{1351, 1666,  1,    4,     8,   0xff,    2,  0},
+	},
+
+	{
+	/*
+	 * memory controller 1
+	 *  lo|  hi|  num|  clk| wrlvl | cpo  |wrdata|2T
+	 * mhz| mhz|ranks|adjst| start |      |delay |
+	 */
+		{  0, 850,    4,    4,     6,   0xff,    2,  0},
+		{851, 950,    4,    5,     7,   0xff,    2,  0},
+		{951, 1050,   4,    5,     8,   0xff,    2,  0},
+		{1051, 1250,  4,    5,    10,   0xff,    2,  0},
+		{1251, 1350,  4,    5,    11,   0xff,    2,  0},
+		{1351, 1666,  4,    5,    12,   0xff,    2,  0},
+		{  0, 850,    2,    4,     6,   0xff,    2,  0},
+		{851, 950,    2,    4,     7,   0xff,    2,  0},
+		{951, 1050,   2,    4,     7,   0xff,    2,  0},
+		{1051, 1250,  2,    4,     8,   0xff,    2,  0},
+		{1251, 1350,  2,    4,     8,   0xff,    2,  0},
+		{1351, 1666,  2,    4,     8,   0xff,    2,  0},
+		{  0, 850,    1,    4,     5,   0xff,    2,  0},
+		{851, 950,    1,    4,     7,   0xff,    2,  0},
+		{951, 1050,   1,    4,     8,   0xff,    2,  0},
+		{1051, 1250,  1,    4,     8,   0xff,    2,  0},
+		{1251, 1350,  1,    4,     8,   0xff,    2,  0},
+		{1351, 1666,  1,    4,     8,   0xff,    2,  0},
 	}
 };
 
@@ -172,13 +230,20 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num)
 {
-	const board_specific_parameters_t *pbsp =
-				&(board_specific_parameters[ctrl_num][0]);
-	u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
-				sizeof(board_specific_parameters[0][0]);
+	const board_specific_parameters_t *pbsp;
+	u32 num_params;
 	u32 i;
 	ulong ddr_freq;
 
+	if (popts->registered_dimm_en) {
+		pbsp = &(board_specific_parameters_rdimm[ctrl_num][0]);
+		num_params = sizeof(board_specific_parameters_rdimm[ctrl_num]) /
+				sizeof(board_specific_parameters_rdimm[0][0]);
+	} else {
+		pbsp = &(board_specific_parameters_udimm[ctrl_num][0]);
+		num_params = sizeof(board_specific_parameters_udimm[ctrl_num]) /
+				sizeof(board_specific_parameters_udimm[0][0]);
+	}
 	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
 	 * freqency and n_banks specified in board_specific_parameters table.
 	 */
@@ -223,20 +288,6 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 
 	/* DHC_EN =1, ODT = 60 Ohm */
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
-
-	/* override SPD values. rcw_2 should vary at differnt speed */
-	if (pdimm[0].registered_dimm == 1) {
-		popts->rcw_override = 1;
-		popts->rcw_1 = 0x000a5a00;
-		if (ddr_freq <= 800)
-			popts->rcw_2 = 0x00000000;
-		else if (ddr_freq <= 1066)
-			popts->rcw_2 = 0x00100000;
-		else if (ddr_freq <= 1333)
-			popts->rcw_2 = 0x00200000;
-		else
-			popts->rcw_2 = 0x00300000;
-	}
 }
 
 phys_size_t initdram(int board_type)