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| author | Matthias Fuchs <matthias.fuchs@esd.eu> | 2009-09-30 11:55:04 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-10-02 13:56:07 +0200 |
| commit | 3b4bd2d75c4b3c1a4570f47ffaaed66f56a78ff4 (patch) | |
| tree | 9b664f63d834af9f5d4b34d93acb16801597c539 /board/esd/pmc440/init.S | |
| parent | fb95169e39f2d03270bed552d27bbb02627a443e (diff) | |
| download | blackbird-obmc-uboot-3b4bd2d75c4b3c1a4570f47ffaaed66f56a78ff4.tar.gz blackbird-obmc-uboot-3b4bd2d75c4b3c1a4570f47ffaaed66f56a78ff4.zip | |
ppc4xx: Add SDRAM detection for PMC440 boards
This patch adds support to detect the amount of DDR2 SDRAM
on PMC440 modules. Detection is done by probing through
a list of available and supported hardware configurations
from 1GByte down to 256MB.
The static TLB entry is replaced by dynamically created entries.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/esd/pmc440/init.S')
| -rw-r--r-- | board/esd/pmc440/init.S | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S index 26a8282cec..6585fed664 100644 --- a/board/esd/pmc440/init.S +++ b/board/esd/pmc440/init.S @@ -23,7 +23,7 @@ #include <asm-ppc/mmu.h> #include <config.h> -/************************************************************************** +/* * TLB TABLE * * This table is used by the cpu boot code to setup the initial tlb @@ -32,7 +32,7 @@ * * Pointer to the table is returned in r1 * - *************************************************************************/ + */ .section .bootpg,"ax" .globl tlbtab @@ -49,12 +49,7 @@ tlbtab: tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) #endif - /* TLB-entry for DDR SDRAM (Up to 2GB) */ -#ifdef CONFIG_4xx_DCACHE - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G) -#else - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) -#endif + /* TLB entries for DDR2 SDRAM are generated dynamically */ #ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
