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authorShengzhou Liu <Shengzhou.Liu@nxp.com>2016-05-04 10:20:21 +0800
committerYork Sun <york.sun@nxp.com>2016-06-03 14:06:35 -0700
commitd8e5163ad81a2810c66a9a98e5111769378f5f5f (patch)
tree0bc10413b7d7ef030566206bba5ff0df5b2046c6 /board/bluegiga
parent8b528709c5bba6a8d0ec83b20545bbd75f082704 (diff)
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drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl
The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series, but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs. We should update it to adapt the case that clk_adjust is odd data. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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