Add support for BC3450 board

Signed-off-by: dzu@denx.de <dzu@denx.de>

6 files changed, 1748 insertions, 0 deletions

diff --git a/board/bc3450/Makefile b/board/bc3450/Makefile
new file mode 100644
index 0000000000..4dec44fd25
--- /dev/null
+++ b/board/bc3450/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o cmd_bc3450.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/bc3450/bc3450.c b/board/bc3450/bc3450.c
new file mode 100644
index 0000000000..a030b82870
--- /dev/null
+++ b/board/bc3450/bc3450.c
@@ -0,0 +1,677 @@
+/*
+ * -- Version 1.1 --
+ *
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004-2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * (C) Copyright 2006
+ * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
+ *
+ * History:
+ *	1.1 - improved SM501 init to meet spec timing
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#ifdef CONFIG_VIDEO_SM501
+#include <sm501.h>
+#endif
+
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m16a2-75.h"
+#endif
+
+#ifdef CONFIG_RTC_MPC5200
+#include <rtc.h>
+#endif 
+
+#ifdef CONFIG_PS2MULT
+void ps2mult_early_init(void);
+#endif
+
+#ifndef CFG_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
+		hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
+		hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
+		hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
+		hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *	      use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *	      is something else than 0x00000000.
+ */
+
+#if defined(CONFIG_MPC5200)
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
+
+	/* find RAM size using SDRAM CS1 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CFG_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CFG_RAMBOOT */
+
+	return dramsize;
+}
+
+#elif defined(CONFIG_MGT5100)
+
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup and enable SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
+	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;	/* 2G		*/
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22);	/* Enable SDRAM */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+
+	/* address select register */
+	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
+	__asm__ volatile ("sync");
+
+	/* find RAM size */
+	sdram_start(0);
+	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* set SDRAM end address according to size */
+	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
+
+#else /* CFG_RAMBOOT */
+
+	/* Retrieve amount of SDRAM available */
+	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
+
+#endif /* CFG_RAMBOOT */
+
+	return dramsize;
+}
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
+
+int checkboard (void)
+{
+#if defined (CONFIG_TQM5200)
+	puts ("Board: TQM5200 (TQ-Components GmbH)\n");
+#endif
+
+#if defined (CONFIG_BC3450)
+	puts ("Dev:   GERSYS BC3450\n");
+#endif
+
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+#if defined(CONFIG_MGT5100)
+	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25);	/* disable CS_BOOT */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16);	/* enable CS0	   */
+#endif
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1;		/* clear RO	   */
+}
+
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+#define GPIO_PSC1_4	0x01000000UL
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA |=  GPIO_PSC1_4;
+	}
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+#ifdef CONFIG_POST
+/*
+ * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
+ * is left open, no keypress is detected.
+ */
+int post_hotkeys_pressed(void)
+{
+	struct mpc5xxx_gpio *gpio;
+
+	gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
+
+	/*
+	 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
+	 * CODEC or UART mode. Consumer IrDA should still be possible.
+	 */
+	gpio->port_config &= ~(0x07000000);
+	gpio->port_config |=   0x03000000;
+
+	/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
+	gpio->simple_gpioe |= 0x20000000;
+
+	/* Configure GPIO_IRDA_1 as input */
+	gpio->simple_ddr &= ~(0x20000000);
+
+	return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
+}
+#endif
+
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+
+void post_word_store (ulong a)
+{
+	volatile ulong *save_addr =
+		(volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
+
+	*save_addr = a;
+}
+
+ulong post_word_load (void)
+{
+	volatile ulong *save_addr =
+		(volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
+
+	return *save_addr;
+}
+#endif	/* CONFIG_POST || CONFIG_LOGBUFFER*/
+
+
+#ifdef CONFIG_BOARD_EARLY_INIT_R
+int board_early_init_r (void)
+{
+#ifdef CONFIG_RTC_MPC5200
+        struct rtc_time t;
+
+	/* set to Wed Dec 31 19:00:00 1969 */
+	t.tm_sec = t.tm_min = 0;
+	t.tm_hour = 19;
+	t.tm_mday = 31;
+	t.tm_mon = 12;
+	t.tm_year = 1969;
+	t.tm_wday = 3;
+	
+	rtc_set(&t);
+#endif /* CONFIG_RTC_MPC5200 */
+
+#ifdef CONFIG_PS2MULT
+	ps2mult_early_init();
+#endif /* CONFIG_PS2MULT */
+	return (0);
+}
+#endif /* CONFIG_BOARD_EARLY_INIT_R */
+
+
+int last_stage_init (void)
+{
+	/*
+	 * auto scan for really existing devices and re-set chip select
+	 * configuration.
+	 */
+	u16 save, tmp;
+	int restore;
+
+	/*
+	 * Check for SRAM and SRAM size
+	 */
+
+	/* save original SRAM content  */
+	save = *(volatile u16 *)CFG_CS2_START;
+	restore = 1;
+
+	/* write test pattern to SRAM */
+	*(volatile u16 *)CFG_CS2_START = 0xA5A5;
+	__asm__ volatile ("sync");
+	/*
+	 * Put a different pattern on the data lines: otherwise they may float
+	 * long enough to read back what we wrote.
+	 */
+	tmp = *(volatile u16 *)CFG_FLASH_BASE;
+	if (tmp == 0xA5A5)
+		puts ("!! possible error in SRAM detection\n");
+
+	if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
+		/* no SRAM at all, disable cs */
+		*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
+		*(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
+		*(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
+		restore = 0;
+		__asm__ volatile ("sync");
+	} else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
+		/* make sure that we access a mirrored address */
+		*(volatile u16 *)CFG_CS2_START = 0x1111;
+		__asm__ volatile ("sync");
+		if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
+			/* SRAM size = 512 kByte */
+			*(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
+								0x80000);
+			__asm__ volatile ("sync");
+			puts ("SRAM:  512 kB\n");
+		}
+		else
+			puts ("!! possible error in SRAM detection\n");
+	} else {
+		puts ("SRAM:  1 MB\n");
+	}
+	/* restore origianl SRAM content  */
+	if (restore) {
+		*(volatile u16 *)CFG_CS2_START = save;
+		__asm__ volatile ("sync");
+	}
+
+	/*
+	 * Check for Grafic Controller
+	 */
+
+	/* save origianl FB content  */
+	save = *(volatile u16 *)CFG_CS1_START;
+	restore = 1;
+
+	/* write test pattern to FB memory */
+	*(volatile u16 *)CFG_CS1_START = 0xA5A5;
+	__asm__ volatile ("sync");
+	/*
+	 * Put a different pattern on the data lines: otherwise they may float
+	 * long enough to read back what we wrote.
+	 */
+	tmp = *(volatile u16 *)CFG_FLASH_BASE;
+	if (tmp == 0xA5A5)
+		puts ("!! possible error in grafic controller detection\n");
+
+	if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
+		/* no grafic controller at all, disable cs */
+		*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
+		*(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
+		*(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
+		restore = 0;
+		__asm__ volatile ("sync");
+	} else {
+		puts ("VGA:   SMI501 (Voyager) with 8 MB\n");
+	}
+	/* restore origianl FB content  */
+	if (restore) {
+		*(volatile u16 *)CFG_CS1_START = save;
+		__asm__ volatile ("sync");
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_VIDEO_SM501
+
+#define DISPLAY_WIDTH   640
+#define DISPLAY_HEIGHT  480
+
+#ifdef CONFIG_VIDEO_SM501_8BPP
+#error CONFIG_VIDEO_SM501_8BPP not supported.
+#endif /* CONFIG_VIDEO_SM501_8BPP */
+
+#ifdef CONFIG_VIDEO_SM501_16BPP
+#error CONFIG_VIDEO_SM501_16BPP not supported.
+#endif /* CONFIG_VIDEO_SM501_16BPP */
+
+#ifdef CONFIG_VIDEO_SM501_32BPP
+static const SMI_REGS init_regs [] =
+{
+#if defined (CONFIG_BC3450_FP) && !defined (CONFIG_BC3450_CRT)
+	/* FP only */
+	{0x00004, 0x0},
+	{0x00048, 0x00021807},
+	{0x0004C, 0x091a0a01},
+	{0x00054, 0x1},
+	{0x00040, 0x00021807},
+	{0x00044, 0x091a0a01},
+	{0x00054, 0x0},
+	{0x80000, 0x01013106},
+	{0x80004, 0xc428bb17},
+	{0x80000, 0x03013106},
+	{0x8000C, 0x00000000},
+	{0x80010, 0x0a000a00},
+	{0x80014, 0x02800000},
+	{0x80018, 0x01e00000},
+	{0x8001C, 0x00000000},
+	{0x80020, 0x01e00280},
+	{0x80024, 0x02fa027f},
+	{0x80028, 0x004a028b},
+	{0x8002C, 0x020c01df},
+	{0x80030, 0x000201e9},
+	{0x80200, 0x00010200},
+	{0x80000, 0x0f013106},
+#elif defined (CONFIG_BC3450_CRT) && !defined (CONFIG_BC3450_FP)
+	/* CRT only */
+	{0x00004, 0x0},
+	{0x00048, 0x00021807},
+	{0x0004C, 0x10090a01},
+	{0x00054, 0x1},
+	{0x00040, 0x00021807},
+	{0x00044, 0x10090a01},
+	{0x00054, 0x0},
+	{0x80200, 0x00010000},
+	{0x80204, 0x0},
+	{0x80208, 0x0A000A00},
+	{0x8020C, 0x02fa027f},
+	{0x80210, 0x004a028b},
+	{0x80214, 0x020c01df},
+	{0x80218, 0x000201e9},
+	{0x80200, 0x00013306},
+#else	/* panel + CRT */
+	{0x00004, 0x0},
+	{0x00048, 0x00021807},
+	{0x0004C, 0x091a0a01},
+	{0x00054, 0x1},
+	{0x00040, 0x00021807},
+	{0x00044, 0x091a0a01},
+	{0x00054, 0x0},
+	{0x80000, 0x0f013106},
+	{0x80004, 0xc428bb17},
+	{0x8000C, 0x00000000},
+	{0x80010, 0x0a000a00},
+	{0x80014, 0x02800000},
+	{0x80018, 0x01e00000},
+	{0x8001C, 0x00000000},
+	{0x80020, 0x01e00280},
+	{0x80024, 0x02fa027f},
+	{0x80028, 0x004a028b},
+	{0x8002C, 0x020c01df},
+	{0x80030, 0x000201e9},
+	{0x80200, 0x00010000},
+#endif
+	{0, 0}
+};
+#endif /* CONFIG_VIDEO_SM501_32BPP */
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+	if (line_number == 1) {
+#if defined (CONFIG_TQM5200)
+	    strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
+#else
+#error No supported board selected
+#endif /* CONFIG_TQM5200 */
+
+#if defined (CONFIG_BC3450)
+	} else if (line_number == 2) {
+	    strcpy (info, " Dev:   GERSYS BC3450");
+#endif /* CONFIG_BC3450 */
+	}
+	else {
+		info [0] = '\0';
+	}
+}
+#endif
+
+/*
+ * Returns SM501 register base address. First thing called in the
+ * driver. Checks if SM501 is physically present.
+ */
+unsigned int board_video_init (void)
+{
+	u16 save, tmp;
+	int restore, ret;
+
+	/*
+	 * Check for Grafic Controller
+	 */
+
+	/* save origianl FB content  */
+	save = *(volatile u16 *)CFG_CS1_START;
+	restore = 1;
+
+	/* write test pattern to FB memory */
+	*(volatile u16 *)CFG_CS1_START = 0xA5A5;
+	__asm__ volatile ("sync");
+	/*
+	 * Put a different pattern on the data lines: otherwise they may float
+	 * long enough to read back what we wrote.
+	 */
+	tmp = *(volatile u16 *)CFG_FLASH_BASE;
+	if (tmp == 0xA5A5)
+		puts ("!! possible error in grafic controller detection\n");
+
+	if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
+		/* no grafic controller found */
+		restore = 0;
+		ret = 0;
+	} else {
+	    ret = SM501_MMIO_BASE;
+	}
+	
+	if (restore) {
+		*(volatile u16 *)CFG_CS1_START = save;
+		__asm__ volatile ("sync");
+	}
+	return ret;
+}
+
+/*
+ * Returns SM501 framebuffer address
+ */
+unsigned int board_video_get_fb (void)
+{
+	return SM501_FB_BASE;
+}
+
+/*
+ * Called after initializing the SM501 and before clearing the screen.
+ */
+void board_validate_screen (unsigned int base)
+{
+}
+
+/*
+ * Return a pointer to the initialization sequence.
+ */
+const SMI_REGS *board_get_regs (void)
+{
+	return init_regs;
+}
+
+int board_get_width (void)
+{
+	return DISPLAY_WIDTH;
+}
+
+int board_get_height (void)
+{
+	return DISPLAY_HEIGHT;
+}
+
+#endif /* CONFIG_VIDEO_SM501 */
diff --git a/board/bc3450/cmd_bc3450.c b/board/bc3450/cmd_bc3450.c
new file mode 100644
index 0000000000..1442b68df1
--- /dev/null
+++ b/board/bc3450/cmd_bc3450.c
@@ -0,0 +1,813 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
+ *
+ * (C) Copyright 2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+/* 
+ * BC3450 specific commands
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+#undef DEBUG
+#ifdef DEBUG
+# define dprintf(fmt,args...)	printf(fmt, ##args)
+#else
+# define dprintf(fmt,args...)
+#endif
+
+/* 
+ * Definitions for DS1620 chip
+ */
+#define THERM_START_CONVERT	0xee
+#define THERM_RESET		0xaf
+#define THERM_READ_CONFIG	0xac
+#define THERM_READ_TEMP		0xaa
+#define THERM_READ_TL		0xa2
+#define THERM_READ_TH		0xa1
+#define THERM_WRITE_CONFIG	0x0c
+#define THERM_WRITE_TL		0x02
+#define THERM_WRITE_TH		0x01
+
+#define CFG_CPU			2
+#define CFG_1SHOT		1
+#define CFG_STANDALONE		0
+
+struct therm {
+    int hi;
+    int lo;
+};
+
+/*
+ * SM501 Register
+ */
+#define SM501_GPIO_CTRL_LOW		0x00000008UL	/* gpio pins 0..31  */
+#define SM501_GPIO_CTRL_HIGH		0x0000000CUL	/* gpio pins 32..63 */
+#define SM501_POWER_MODE0_GATE		0x00000040UL
+#define SM501_POWER_MODE1_GATE		0x00000048UL
+#define POWER_MODE_GATE_GPIO_PWM_I2C	0x00000040UL
+#define SM501_GPIO_DATA_LOW 		0x00010000UL
+#define SM501_GPIO_DATA_HIGH		0x00010004UL
+#define SM501_GPIO_DATA_DIR_LOW		0x00010008UL
+#define SM501_GPIO_DATA_DIR_HIGH	0x0001000CUL
+#define SM501_PANEL_DISPLAY_CONTROL	0x00080000UL
+#define SM501_CRT_DISPLAY_CONTROL	0x00080200UL
+
+/* SM501 CRT Display Control Bits */
+#define SM501_CDC_SEL			(1 << 9)
+#define SM501_CDC_TE			(1 << 8)
+#define SM501_CDC_E			(1 << 2)
+
+/* SM501 Panel Display Control Bits */
+#define SM501_PDC_FPEN			(1 << 27)
+#define SM501_PDC_BIAS			(1 << 26)
+#define SM501_PDC_DATA			(1 << 25)
+#define SM501_PDC_VDDEN			(1 << 24)
+
+/* SM501 GPIO Data LOW Bits */
+#define SM501_GPIO24			0x01000000
+#define SM501_GPIO25			0x02000000
+#define SM501_GPIO26			0x04000000
+#define SM501_GPIO27			0x08000000
+#define SM501_GPIO28			0x10000000
+#define SM501_GPIO29			0x20000000
+#define SM501_GPIO30			0x40000000
+#define SM501_GPIO31			0x80000000
+
+/* SM501 GPIO Data HIGH Bits */
+#define SM501_GPIO46			0x00004000
+#define SM501_GPIO47			0x00008000
+#define SM501_GPIO48			0x00010000
+#define SM501_GPIO49			0x00020000
+#define SM501_GPIO50			0x00040000
+#define SM501_GPIO51			0x00080000
+
+/* BC3450 GPIOs @ SM501 Data LOW */
+#define DIP				(SM501_GPIO24 | SM501_GPIO25 | SM501_GPIO26 | SM501_GPIO27)
+#define DS1620_DQ			SM501_GPIO29	/* I/O             */
+#define DS1620_CLK			SM501_GPIO30	/* High active O/P */
+#define DS1620_RES			SM501_GPIO31	/* Low active O/P  */
+/* BC3450 GPIOs @ SM501 Data HIGH */
+#define BUZZER				SM501_GPIO47	/* Low active O/P  */
+#define DS1620_TLOW			SM501_GPIO48	/* High active I/P */
+#define PWR_OFF				SM501_GPIO49	/* Low active O/P  */
+#define FP_DATA_TRI			SM501_GPIO50	/* High active O/P */
+
+
+/*
+ * Initialise GPIO on SM501
+ *
+ * This function may be called from several other functions.
+ * Yet, the initialisation sequence is executed only the first
+ * time the function is called.
+ */
+int sm501_gpio_init(void)
+{
+    static int init_done = 0;
+
+    if(init_done) {
+/*	dprintf("sm501_gpio_init: nothing to be done.\n"); */
+	return 1;
+    }
+
+    /* enable SM501 GPIO control (in both power modes) */
+    *(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE0_GATE) |= POWER_MODE_GATE_GPIO_PWM_I2C;
+    *(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE1_GATE) |= POWER_MODE_GATE_GPIO_PWM_I2C;
+
+    /* set up default O/Ps */
+    *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~(DS1620_RES | DS1620_CLK);
+    *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_DQ;
+    *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &= ~(FP_DATA_TRI);
+    *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |= (BUZZER | PWR_OFF);
+
+    /* configure directions for SM501 GPIO pins */
+    *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_LOW) &= ~(0xFF << 24);
+    *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_HIGH) &= ~(0x3F << 14);
+    *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &= ~(DIP | DS1620_DQ);
+    *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |= (DS1620_RES | DS1620_CLK);
+    *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) &= ~DS1620_TLOW;
+    *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) |= (PWR_OFF | BUZZER | FP_DATA_TRI);
+
+    init_done = 1;
+/*  dprintf("sm501_gpio_init: done.\n"); */
+    return 0;
+}
+
+
+/*
+ * dip - read Config Inputs
+ *
+ * read and prints the dip switch
+ * and/or external config inputs (4bits) 0...0x0F
+ */
+int cmd_dip (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+    vu_long rc = 0;
+
+    sm501_gpio_init();
+
+    /* read dip switch */
+    rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW);
+    rc = ~rc;
+    rc &= DIP;
+    rc = (int)(rc >> 24);
+
+    /* plausibility check */
+    if (rc > 0x0F)
+	return -1;
+
+    printf ("0x%x\n", rc);
+    return 0;
+}
+
+U_BOOT_CMD(
+	dip ,	1,	1,	cmd_dip,
+	"dip     - read dip switch and config inputs\n",
+	"\n"
+	"     - prints the state of the dip switch and/or\n"
+	"       external configuration inputs as hex value.\n"
+	"     - \"Config 1\" is the LSB\n"
+    );
+
+
+/*
+ * buz - turns Buzzer on/off
+ */
+#ifdef CONFIG_BC3450_BUZZER
+static int cmd_buz (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+    if (argc != 2) {
+	printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n");
+	return 1;
+    }
+
+    sm501_gpio_init();
+
+    if (strncmp (argv[1], "on", 2) == 0) {
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &= ~(BUZZER);
+	return 0;
+    }
+    else if (strncmp (argv[1], "off", 3) == 0) {
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |= BUZZER;
+	return 0;
+    }
+    printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n");
+    return 1;
+}
+
+U_BOOT_CMD(
+	buz ,	2,	1,	cmd_buz,
+	"buz     - turns buzzer on/off\n",
+	"\n"
+	"buz <on/off>\n"
+	"     - turns the buzzer on or off\n"
+    );
+#endif /* CONFIG_BC3450_BUZZER */
+
+
+/*
+ * fp - front panel commands
+ */
+static int cmd_fp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+    sm501_gpio_init();
+
+    if (strncmp (argv[1], "on", 2) == 0) {
+	/* turn on VDD first */
+	*(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_VDDEN;
+	udelay(1000);
+	/* then put data on */
+	*(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_DATA;
+	/* wait some time and enable backlight */
+	udelay(1000);
+	*(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_BIAS;
+	udelay(1000);
+	*(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_FPEN;
+	return 0;
+    }
+    else if (strncmp (argv[1], "off", 3) == 0) {
+	/* turn off the backlight first */
+	*(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_FPEN;
+	udelay(1000);
+	*(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_BIAS;
+	udelay(200000);
+	/* wait some time, then remove data */
+	*(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_DATA;
+	udelay(1000);
+	/* and remove VDD last */
+	*(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_VDDEN;
+	return 0;
+    }
+    else if (strncmp (argv[1], "bl", 2) == 0) {
+	/* turn on/off backlight only */
+	if (strncmp (argv[2], "on", 2) == 0) {
+	    *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_BIAS;
+	    udelay(1000);
+	    *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_FPEN;
+	    return 0;
+	}
+	else if (strncmp (argv[2], "off", 3) == 0) {
+	    *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_FPEN;
+	    udelay(1000);
+	    *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_BIAS;
+	    return 0;
+	}
+    }
+#ifdef CONFIG_BC3450_CRT
+    else if (strncmp (argv[1], "crt", 3) == 0) {
+	/* enables/disables the crt output (debug only) */
+	if(strncmp (argv[2], "on", 2) == 0) {
+	    *(vu_long *)(SM501_MMIO_BASE + SM501_CRT_DISPLAY_CONTROL) |= 
+		(SM501_CDC_TE | SM501_CDC_E);
+	    *(vu_long *)(SM501_MMIO_BASE + SM501_CRT_DISPLAY_CONTROL) &= 
+		~SM501_CDC_SEL;
+	    return 0;
+	}
+	else if (strncmp (argv[2], "off", 3) == 0) {
+	    *(vu_long *)(SM501_MMIO_BASE + SM501_CRT_DISPLAY_CONTROL) &= 
+		~(SM501_CDC_TE | SM501_CDC_E);
+	    *(vu_long *)(SM501_MMIO_BASE + SM501_CRT_DISPLAY_CONTROL) |= 
+		SM501_CDC_SEL;
+	    return 0;
+	}
+    }
+#endif /* CONFIG_BC3450_CRT */
+    printf("Usage:%s\n", cmdtp->help);
+    return 1;
+}
+
+U_BOOT_CMD(
+	fp ,	3,	1,	cmd_fp,
+	"fp      - front panes access functions\n",
+	"\n"
+	"fp bl <on/off>\n"
+	"     - turns the CCFL backlight of the display on/off\n"
+	"fp <on/off>\n"
+	"     - turns the whole display on/off\n"
+#ifdef CONFIG_BC3450_CRT
+	"fp crt <on/off>\n"
+	"     - enables/disables the crt output (debug only)\n"
+#endif /* CONFIG_BC3450_CRT */
+    );
+
+
+/*
+ * temp - DS1620 thermometer
+ */
+/* GERSYS BC3450 specific functions */
+static inline void bc_ds1620_set_clk(int clk)
+{
+    if(clk)
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_CLK;
+    else
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~DS1620_CLK;
+}
+
+static inline void bc_ds1620_set_data(int dat)
+{
+    if(dat)
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_DQ;
+    else
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~DS1620_DQ;
+}
+
+static inline int bc_ds1620_get_data(void)
+{
+    vu_long rc;
+    rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW);
+    rc &= DS1620_DQ;
+    if(rc != 0)
+	rc = 1;
+    return (int)rc;
+}
+
+static inline void bc_ds1620_set_data_dir(int dir)
+{
+    if(dir) /* in */
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &= ~DS1620_DQ;
+    else /* out */
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |= DS1620_DQ;
+}
+
+static inline void bc_ds1620_set_reset(int res)
+{
+    if(res)
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_RES;
+    else
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~DS1620_RES;
+}
+
+/* hardware independent functions */
+static void ds1620_send_bits(int nr, int value)
+{
+    int i;
+    
+    for (i = 0; i < nr; i++) {
+	bc_ds1620_set_data(value & 1);
+	bc_ds1620_set_clk(0);
+	udelay(1);
+	bc_ds1620_set_clk(1);
+	udelay(1);
+	
+	value >>= 1;
+    }
+}
+
+static unsigned int ds1620_recv_bits(int nr)
+{
+    unsigned int value = 0, mask = 1;
+    int i;
+
+    bc_ds1620_set_data(0);
+
+    for (i = 0; i < nr; i++) {
+	bc_ds1620_set_clk(0);
+	udelay(1);
+
+	if (bc_ds1620_get_data())
+	    value |= mask;
+
+	mask <<= 1;
+
+	bc_ds1620_set_clk(1);
+	udelay(1);
+    }
+
+    return value;
+}
+
+static void ds1620_out(int cmd, int bits, int value)
+{
+    bc_ds1620_set_clk(1);
+    bc_ds1620_set_data_dir(0);
+
+    bc_ds1620_set_reset(0);
+    udelay(1);
+    bc_ds1620_set_reset(1);
+
+    udelay(1);
+
+    ds1620_send_bits(8, cmd);
+    if (bits)
+	ds1620_send_bits(bits, value);
+
+    udelay(1);
+
+    /* go stand alone */
+    bc_ds1620_set_data_dir(1);
+    bc_ds1620_set_reset(0);
+    bc_ds1620_set_clk(0);
+
+    udelay(10000);
+}
+
+static unsigned int ds1620_in(int cmd, int bits)
+{
+    unsigned int value;
+
+    bc_ds1620_set_clk(1);
+    bc_ds1620_set_data_dir(0);
+
+    bc_ds1620_set_reset(0);
+    udelay(1);
+    bc_ds1620_set_reset(1);
+
+    udelay(1);
+
+    ds1620_send_bits(8, cmd);
+
+    bc_ds1620_set_data_dir(1);
+    value = ds1620_recv_bits(bits);
+
+    /* go stand alone */
+    bc_ds1620_set_data_dir(1);
+    bc_ds1620_set_reset(0);
+    bc_ds1620_set_clk(0);
+
+    return value;
+}
+
+static int cvt_9_to_int(unsigned int val)
+{
+    if (val & 0x100)
+	val |= 0xfffffe00;
+
+    return val;
+}
+
+/* set thermostate thresholds */
+static void ds1620_write_state(struct therm *therm)
+{
+    ds1620_out(THERM_WRITE_TL, 9, therm->lo);
+    ds1620_out(THERM_WRITE_TH, 9, therm->hi);
+    ds1620_out(THERM_START_CONVERT, 0, 0);
+}
+
+static int cmd_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+    int i;
+    struct therm therm;
+
+    sm501_gpio_init();
+
+    /* print temperature */
+    if (argc == 1) {
+	i = cvt_9_to_int(ds1620_in(THERM_READ_TEMP, 9));
+	printf("%d.%d C\n", i >> 1, i & 1 ? 5 : 0);
+	return 0;
+    }
+
+    /* set to default operation */
+    if (strncmp (argv[1], "set", 3) == 0) {
+	if(strncmp (argv[2], "default", 3) == 0) {
+	    therm.hi = +88;
+	    therm.lo = -20;
+	    therm.hi <<= 1;
+	    therm.lo <<= 1;
+	    ds1620_write_state(&therm);
+	    ds1620_out(THERM_WRITE_CONFIG, 8, CFG_STANDALONE);
+	    return 0;
+	}
+    }
+
+    printf ("Usage:%s\n", cmdtp->help);
+    return 1;
+}
+
+U_BOOT_CMD(
+	temp ,	3,	1,	cmd_temp,
+	"temp    - print current temperature\n",
+	"\n"
+	"temp\n"
+	"     - print current temperature\n"
+);
+
+#ifdef CONFIG_BC3450_CAN
+/*
+ * Initialise CAN interface
+ *
+ * return 1 on CAN initialization failure
+ * return 0 if no failure
+ */
+int can_init(void)
+{
+	static int init_done = 0;
+	int i;
+	struct mpc5xxx_mscan *can1 =
+		(struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900);
+	struct mpc5xxx_mscan *can2 =
+		(struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980);
+
+	/* GPIO configuration of the CAN pins is done in BC3450.h */
+
+	if (!init_done) {
+		/* init CAN 1 */
+		can1->canctl1 |= 0x80;	/* CAN enable */
+		udelay(100);
+
+		i = 0;
+		can1->canctl0 |= 0x02;	/* sleep mode */
+		/* wait until sleep mode reached */
+		while (!(can1->canctl1 & 0x02)) {
+			udelay(10);
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN1 initialize error, "
+				"can not enter sleep mode!\n",
+				__FUNCTION__);
+			return 1;
+		}
+		}
+		i = 0;
+		can1->canctl0 = 0x01;	/* enter init mode */
+		/* wait until init mode reached */
+		while (!(can1->canctl1 & 0x01)) {
+			udelay(10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN1 initialize error, "
+					"can not enter init mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		can1->canctl1 = 0x80;
+		can1->canctl1 |= 0x40;
+		can1->canbtr0 = 0x0F;
+		can1->canbtr1 = 0x7F;
+		can1->canidac &= ~(0x30);
+		can1->canidar1 = 0x00;
+		can1->canidar3 = 0x00;
+		can1->canidar5 = 0x00;
+		can1->canidar7 = 0x00;
+		can1->canidmr0 = 0xFF;
+		can1->canidmr1 = 0xFF;
+		can1->canidmr2 = 0xFF;
+		can1->canidmr3 = 0xFF;
+		can1->canidmr4 = 0xFF;
+		can1->canidmr5 = 0xFF;
+		can1->canidmr6 = 0xFF;
+		can1->canidmr7 = 0xFF;
+
+		i = 0;
+		can1->canctl0 &= ~(0x01);	/* leave init mode */
+		can1->canctl0 &= ~(0x02);
+		/* wait until init and sleep mode left */
+		while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) {
+			udelay(10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN1 initialize error, "
+					"can not leave init/sleep mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+
+		/* init CAN 2 */
+		can2->canctl1 |= 0x80;	/* CAN enable */
+		udelay(100);
+
+		i = 0;
+		can2->canctl0 |= 0x02;	/* sleep mode */
+		/* wait until sleep mode reached */
+		while (!(can2->canctl1 & 0x02))	{
+			udelay(10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN2 initialize error, "
+					"can not enter sleep mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		i = 0;
+		can2->canctl0 = 0x01;	/* enter init mode */
+		/* wait until init mode reached */
+		while (!(can2->canctl1 & 0x01))	{
+			udelay(10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN2 initialize error, "
+					"can not enter init mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		can2->canctl1 = 0x80;
+		can2->canctl1 |= 0x40;
+		can2->canbtr0 = 0x0F;
+		can2->canbtr1 = 0x7F;
+		can2->canidac &= ~(0x30);
+		can2->canidar1 = 0x00;
+		can2->canidar3 = 0x00;
+		can2->canidar5 = 0x00;
+		can2->canidar7 = 0x00;
+		can2->canidmr0 = 0xFF;
+		can2->canidmr1 = 0xFF;
+		can2->canidmr2 = 0xFF;
+		can2->canidmr3 = 0xFF;
+		can2->canidmr4 = 0xFF;
+		can2->canidmr5 = 0xFF;
+		can2->canidmr6 = 0xFF;
+		can2->canidmr7 = 0xFF;
+		can2->canctl0 &= ~(0x01);	/* leave init mode */
+		can2->canctl0 &= ~(0x02);
+
+		i = 0;
+		/* wait until init mode left */
+		while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) {
+			udelay(10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN2 initialize error, "
+					"can not leave init/sleep mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		init_done = 1;
+	}
+	return 0;
+}
+
+/*
+ * Do CAN test
+ * by sending message between CAN1 and CAN2
+ *
+ * return 1 on CAN failure
+ * return 0 if no failure
+ */
+int do_can(char *argv[])
+{
+	int i;
+	struct mpc5xxx_mscan *can1 = 
+		(struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900);
+	struct mpc5xxx_mscan *can2 = 
+		(struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980);
+
+	/* send a message on CAN1 */
+	can1->cantbsel = 0x01;
+	can1->cantxfg.idr[0] = 0x55;
+	can1->cantxfg.idr[1] = 0x00;
+	can1->cantxfg.idr[1] &= ~0x8;
+	can1->cantxfg.idr[1] &= ~0x10;
+	can1->cantxfg.dsr[0] = 0xCC;
+	can1->cantxfg.dlr = 1;
+	can1->cantxfg.tbpr = 0;
+	can1->cantflg = 0x01;
+
+	i = 0;
+	while ((can1->cantflg & 0x01) == 0) {
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN1 send timeout, "
+				"can not send message!\n",
+				__FUNCTION__);
+			return 1;
+		}
+		udelay(1000);
+	}
+	udelay(1000);
+
+	i = 0;
+	while (!(can2->canrflg & 0x01))	{
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN2 receive timeout, "
+				"no message received!\n",
+				__FUNCTION__);
+			return 1;
+		}
+		udelay(1000);
+	}
+	
+	if (can2->canrxfg.dsr[0] != 0xCC) {
+		printf ("%s: CAN2 receive error, "
+			 "data mismatch!\n",
+			__FUNCTION__);
+		return 1;
+	}
+
+	/* send a message on CAN2 */
+	can2->cantbsel = 0x01;
+	can2->cantxfg.idr[0] = 0x55;
+	can2->cantxfg.idr[1] = 0x00;
+	can2->cantxfg.idr[1] &= ~0x8;
+	can2->cantxfg.idr[1] &= ~0x10;
+	can2->cantxfg.dsr[0] = 0xCC;
+	can2->cantxfg.dlr = 1;
+	can2->cantxfg.tbpr = 0;
+	can2->cantflg = 0x01;
+
+	i = 0;
+	while ((can2->cantflg & 0x01) == 0) {
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN2 send error, "
+				"can not send message!\n",
+				__FUNCTION__);
+			return 1;
+		}
+		udelay(1000);
+	}
+	udelay(1000);
+
+	i = 0;
+	while (!(can1->canrflg & 0x01))	{
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN1 receive timeout, "
+				"no message received!\n",
+				__FUNCTION__);
+			return 1;
+		}
+		udelay(1000);
+	}
+
+	if (can1->canrxfg.dsr[0] != 0xCC) {
+		printf ("%s: CAN1 receive error 0x%02x\n",
+			__FUNCTION__, (can1->canrxfg.dsr[0]));
+		return 1;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_BC3450_CAN */
+
+/*
+ * test - BC3450 HW test routines
+ */
+int cmd_test(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+#ifdef CONFIG_BC3450_CAN
+    int rcode;
+    can_init();
+#endif /* CONFIG_BC3450_CAN */
+
+    sm501_gpio_init();
+
+    if (argc != 2) {
+	printf ("Usage:%s\n", cmdtp->help);
+	return 1;
+    }
+
+    if (strncmp (argv[1], "unit-off", 8) == 0) {
+	printf ("waiting 2 seconds...\n");
+	udelay(2000000);
+	*(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &= ~PWR_OFF;
+	return 0;
+    }
+#ifdef CONFIG_BC3450_CAN
+    else if (strncmp (argv[1], "can", 2) == 0) {
+	rcode = do_can (argv);
+	if (simple_strtoul(argv[2], NULL, 10) == 2) {
+	    if (rcode == 0)
+		printf ("OK\n");
+	    else
+		printf ("Error\n");
+	}
+	return rcode;
+    }
+#endif /* CONFIG_BC3450_CAN */
+
+    printf ("Usage:%s\n", cmdtp->help);
+    return 1;
+}
+
+U_BOOT_CMD(
+	test ,	2,	1,	cmd_test,
+	"test    - unit test routines\n",
+	"\n"
+#ifdef CONFIG_BC3450_CAN
+	"test can\n"
+	"     - connect CAN1 (X8) with CAN2 (X9) for this test\n"
+#endif /* CONFIG_BC3450_CAN */
+	"test unit-off\n"
+	"     - turns off the BC3450 unit\n"
+	"       WARNING: Unsaved environment variables will be lost!\n"
+    );
+#endif /* CFG_CMD_BSP */
diff --git a/board/bc3450/config.mk b/board/bc3450/config.mk
new file mode 100644
index 0000000000..47e9955789
--- /dev/null
+++ b/board/bc3450/config.mk
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# BC3450 board:
+#
+#	Valid values for TEXT_BASE are:
+#
+#	0xFC000000   boot low (standard configuration with room for max 64 MByte
+#		     Flash ROM)
+#	0x00100000   boot from RAM (for testing only)
+#
+
+ifndef TEXT_BASE
+## Standard: boot low
+TEXT_BASE = 0xFC000000
+## For testing: boot from RAM
+# TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/bc3450/mt48lc16m16a2-75.h b/board/bc3450/mt48lc16m16a2-75.h
new file mode 100644
index 0000000000..3f1e1691bb
--- /dev/null
+++ b/board/bc3450/mt48lc16m16a2-75.h
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+/* #define SDRAM_MODE	0x008D0000 */ /* CAS latency 2 */
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+/* #define SDRAM_CONFIG1	0xD2222800 */ /* CAS latency 2 */
+/*#define SDRAM_CONFIG1	0xD7322800 */ /* SDRAM controller bug workaround */
+#define SDRAM_CONFIG2	0x8AD70000
+/*#define SDRAM_CONFIG2	0xDDD70000 */ /* SDRAM controller bug workaround */
+
+#elif defined(CONFIG_MGT5100)
+/* Settings for XLB = 66 MHz */
+#define SDRAM_MODE	0x008D0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xC2222600
+#define SDRAM_CONFIG2	0x88B70004
+#define SDRAM_ADDRSEL	0x02000000
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
diff --git a/board/bc3450/u-boot.lds b/board/bc3450/u-boot.lds
new file mode 100644
index 0000000000..93b98a8f5c
--- /dev/null
+++ b/board/bc3450/u-boot.lds
@@ -0,0 +1,124 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}