Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm:
  ARM: MX5: Fix broken leftover TO-2 errata workaround
  MX31: Cleanup clock function
  scb9328: Add ARM relocation support
  am3517evm: change console device from ttyS2 to ttyO2
  Remove volatile qualifier in get_ram_size() calls
  TI: TNETV107X Fix Build Error
  ARM: add missing CONFIG_SKIP_LOWLEVEL_INIT for armv7
  arm: add CONFIG_MACH_TYPE setting and documentation
  arm: add __ilog2 function
  Timer: Fix misuse of ARM *timer_masked() functions outside arch/arm
  EfikaMX: Enable EXT2 booting
  EfikaMX: Add missing CONFIG_SYS_TEXT_BASE
  EfikaMX: Use correct imximage.cfg
  MX27: Update to autogenerated asm-offsets.h
  MX5: Update to autogenerated asm-offsets.h
  imx: Add support for zmx25 board
  imx: Make imx25 compatible to mxc_gpio driver and fix in tx25
  imx: Add auto generation of asm-offsets.h for imx25
  imx: Add support for USB EHCI on imx25
  imx: Use correct imx25 reset.c
  imx: Add get_tbclk() function for imx25
  ARM: Update maintainer of board scb9328
  mx27: Make the UART port number explicit
  build: Add targets for auto gen of asm-offsets.h and use it in imx35
  mx31pdk: cosmetic: Fix line over 80 characters

23 files changed, 380 insertions, 97 deletions

diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c
index 4ebf38d765..248431b9bc 100644
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ b/arch/arm/cpu/arm1136/mx31/generic.c
@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
 #include <asm/io.h>
 
 static u32 mx31_decode_pll(u32 reg, u32 infreq)
@@ -60,7 +61,7 @@ static u32 mx31_get_mcu_main_clk(void)
 	return mx31_get_mpl_dpdgck_clk();
 }
 
-u32 mx31_get_ipg_clk(void)
+static u32 mx31_get_ipg_clk(void)
 {
 	u32 freq = mx31_get_mcu_main_clk();
 	u32 pdr0 = __REG(CCM_PDR0);
@@ -78,6 +79,24 @@ void mx31_dump_clocks(void)
 	printf("ipg clock     : %dHz\n", mx31_get_ipg_clk());
 }
 
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return mx31_get_mcu_main_clk();
+	case MXC_IPG_CLK:
+	case MXC_CSPI_CLK:
+	case MXC_UART_CLK:
+		return mx31_get_ipg_clk();
+	}
+	return -1;
+}
+
+u32 imx_get_uartclk(void)
+{
+	return mxc_get_clock(MXC_UART_CLK);
+}
+
 void mx31_gpio_mux(unsigned long mode)
 {
 	unsigned long reg, shift, tmp;
diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile
index 20f36e3e0e..284cdc50d1 100644
--- a/arch/arm/cpu/arm1136/mx35/Makefile
+++ b/arch/arm/cpu/arm1136/mx35/Makefile
@@ -50,14 +50,3 @@ include $(SRCTREE)/rules.mk
 sinclude $(obj).depend
 
 #########################################################################
-
-$(TOPDIR)/include/asm/arch/asm-offsets.h:	$(TOPDIR)/include/autoconf.mk.dep \
-	./asm-offsets.s
-	@echo Generating $@
-	$(TOPDIR)/tools/scripts/make-asm-offsets ./asm-offsets.s $@
-
-asm-offsets.s:	$(TOPDIR)/include/autoconf.mk.dep \
-	./asm-offsets.c
-	$(CC) -DDO_DEPS_ONLY \
-		$(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
-		-o $@ ./asm-offsets.c -c -S
diff --git a/arch/arm/cpu/arm926ejs/mx25/Makefile b/arch/arm/cpu/arm926ejs/mx25/Makefile
index 38d7f03ab2..9219c062b0 100644
--- a/arch/arm/cpu/arm926ejs/mx25/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx25/Makefile
@@ -24,18 +24,18 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS	= generic.o timer.o
-MX27OBJS = reset.o
+COBJS	= generic.o timer.o reset.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-SRCS	+= $(addprefix $(SRCTREE)/arch/arm/cpu/arm926ejs/mx27/,$(MX27OBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS) $(MX27OBJS))
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
 
 all:	$(obj).depend $(LIB)
 
 $(LIB):	$(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
 
+$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h
+
 #########################################################################
 
 # defines $(obj).depend target
diff --git a/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c
new file mode 100644
index 0000000000..ba8dfd4228
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c
@@ -0,0 +1,60 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+	/* Clock Control Module */
+	DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
+	DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
+	DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
+	DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
+	DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
+	DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
+
+	/* Enhanced SDRAM Controller */
+	DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
+	DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
+	DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
+
+	/* Multi-Layer AHB Crossbar Switch */
+	DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
+	DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
+	DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
+	DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
+	DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
+	DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
+	DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
+	DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
+	DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
+	DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
+	DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
+	DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
+	DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
+	DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
+	DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
+
+	/* AHB <-> IP-Bus Interface */
+	DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
+	DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
+
+	return 0;
+}
diff --git a/arch/arm/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c
index 14f0c2dc73..7c8a71b9d3 100644
--- a/arch/arm/cpu/arm926ejs/mx25/timer.c
+++ b/arch/arm/cpu/arm926ejs/mx25/timer.c
@@ -187,3 +187,15 @@ void __udelay (unsigned long usec)
 	while (get_ticks() < tmp)	/* loop till event */
 		 /*NOP*/;
 }
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	ulong tbclk;
+
+	tbclk = CONFIG_MX25_CLK32;
+	return tbclk;
+}
diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile b/arch/arm/cpu/arm926ejs/mx27/Makefile
index 0e112b34f4..7ac1a21406 100644
--- a/arch/arm/cpu/arm926ejs/mx27/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx27/Makefile
@@ -34,6 +34,8 @@ all:	$(obj).depend $(LIB)
 $(LIB):	$(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
 
+$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h
+
 #########################################################################
 
 # defines $(obj).depend target
diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
new file mode 100644
index 0000000000..f3a8d7bd69
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
@@ -0,0 +1,45 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+	DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
+	DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
+	DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
+	DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
+
+	DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
+	DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
+	DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
+	DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
+	DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
+	DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
+	DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
+
+	DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
+	DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
+	DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
+	DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
+	DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
+
+	return 0;
+}
diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c
index 27642bfe7d..222a8e95ea 100644
--- a/arch/arm/cpu/arm926ejs/mx27/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx27/generic.c
@@ -271,7 +271,7 @@ void imx_gpio_mode(int gpio_mode)
 }
 
 #ifdef CONFIG_MXC_UART
-void mx27_uart_init_pins(void)
+void mx27_uart1_init_pins(void)
 {
 	int i;
 	unsigned int mode[] = {
diff --git a/arch/arm/cpu/arm926ejs/orion5x/dram.c b/arch/arm/cpu/arm926ejs/orion5x/dram.c
index 3e1ff7d8ea..5cc31a99f1 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/dram.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/dram.c
@@ -53,7 +53,7 @@ int dram_init (void)
 {
 	/* dram_init must store complete ramsize in gd->ram_size */
 	gd->ram_size = get_ram_size(
-			(volatile long *) orion5x_sdram_bar(0),
+			(long *) orion5x_sdram_bar(0),
 			CONFIG_MAX_RAM_BANK_SIZE);
 	return 0;
 }
@@ -65,7 +65,7 @@ void dram_init_banksize (void)
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 		gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
 		gd->bd->bi_dram[i].size = get_ram_size(
-			(volatile long *) (gd->bd->bi_dram[i].start),
+			(long *) (gd->bd->bi_dram[i].start),
 			CONFIG_MAX_RAM_BANK_SIZE);
 	}
 }
diff --git a/arch/arm/cpu/armv7/mx5/Makefile b/arch/arm/cpu/armv7/mx5/Makefile
index e8be9c9fab..6e13cc3e84 100644
--- a/arch/arm/cpu/armv7/mx5/Makefile
+++ b/arch/arm/cpu/armv7/mx5/Makefile
@@ -45,4 +45,6 @@ include $(SRCTREE)/rules.mk
 
 sinclude $(obj).depend
 
+lowlevel_init.o : $(TOPDIR)/include/asm/arch/asm-offsets.h
+
 #########################################################################
diff --git a/arch/arm/cpu/armv7/mx5/asm-offsets.c b/arch/arm/cpu/armv7/mx5/asm-offsets.c
new file mode 100644
index 0000000000..f97249899d
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx5/asm-offsets.c
@@ -0,0 +1,76 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+
+	/* Round up to make sure size gives nice stack alignment */
+	DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
+	DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
+	DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
+	DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
+	DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
+	DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
+	DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
+	DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
+	DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
+	DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
+	DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
+	DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
+	DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
+	DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
+	DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
+	DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
+	DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
+	DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
+	DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
+	DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
+	DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
+	DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
+	DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
+	DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
+	DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
+	DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
+	DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
+	DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
+	DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
+	DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
+	DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
+	DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
+	DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
+	DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
+#if defined(CONFIG_MX53)
+	DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
+#endif
+
+	/* DPLL */
+	DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
+	DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
+	DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
+	DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
+	DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
+	DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
+	DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
+	DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 96ebfe2345..94de9f1d61 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -39,10 +39,14 @@
 	orr r0, r0, #(1 << 23)		/* disable write allocate combine */
 	orr r0, r0, #(1 << 22)		/* disable write allocate */
 
-	cmp r3, #0x10    /* r3 contains the silicon rev */
+#if defined(CONFIG_MX51)
+	ldr r1, =0x0
+	ldr r3, [r1, #ROM_SI_REV]
+	cmp r3, #0x10
 
 	/* disable write combine for TO 2 and lower revs */
 	orrls r0, r0, #(1 << 25)
+#endif
 
 	mcr 15, 1, r0, c9, c0, 2
 .endm /* init_l2cc */
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 0e698b624b..eee648bdc4 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -283,6 +283,7 @@ _rel_dyn_end_ofs:
 _dynsym_start_ofs:
 	.word __dynsym_start - _start
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 /*************************************************************************
  *
  * CPU_init_critical registers
@@ -327,6 +328,7 @@ cpu_init_crit:
 	bl	lowlevel_init		@ go setup pll,mux,memory
 	mov	lr, ip			@ restore link
 	mov	pc, lr			@ back to my caller
+#endif
 /*
  *************************************************************************
  *
diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
index 55ad115a76..2ccb445975 100644
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -86,8 +86,8 @@ struct esdramc_regs {
 
 /* GPIO registers */
 struct gpio_regs {
-	u32 dr;		/* data */
-	u32 dir;	/* direction */
+	u32 gpio_dr;	/* data */
+	u32 gpio_dir;	/* direction */
 	u32 psr;	/* pad satus */
 	u32 icr1;	/* interrupt config 1 */
 	u32 icr2;	/* interrupt config 2 */
@@ -141,6 +141,45 @@ struct fuse_bank0_regs {
 	u32 mac_addr[6];
 };
 
+/* Multi-Layer AHB Crossbar Switch (MAX) registers */
+struct max_regs {
+	u32 mpr0;
+	u32 pad00[3];
+	u32 sgpcr0;
+	u32 pad01[59];
+	u32 mpr1;
+	u32 pad02[3];
+	u32 sgpcr1;
+	u32 pad03[59];
+	u32 mpr2;
+	u32 pad04[3];
+	u32 sgpcr2;
+	u32 pad05[59];
+	u32 mpr3;
+	u32 pad06[3];
+	u32 sgpcr3;
+	u32 pad07[59];
+	u32 mpr4;
+	u32 pad08[3];
+	u32 sgpcr4;
+	u32 pad09[251];
+	u32 mgpcr0;
+	u32 pad10[63];
+	u32 mgpcr1;
+	u32 pad11[63];
+	u32 mgpcr2;
+	u32 pad12[63];
+	u32 mgpcr3;
+	u32 pad13[63];
+	u32 mgpcr4;
+};
+
+/* AHB <-> IP-Bus Interface (AIPS) */
+struct aips_regs {
+	u32 mpr_0_7;
+	u32 mpr_8_15;
+};
+
 #endif
 
 /* AIPS 1 */
@@ -318,4 +357,10 @@ struct fuse_bank0_regs {
 #define WSR_UNLOCK1		0x5555
 #define WSR_UNLOCK2		0xAAAA
 
+/* Names used in GPIO driver */
+#define GPIO1_BASE_ADDR		IMX_GPIO1_BASE
+#define GPIO2_BASE_ADDR		IMX_GPIO2_BASE
+#define GPIO3_BASE_ADDR		IMX_GPIO3_BASE
+#define GPIO4_BASE_ADDR		IMX_GPIO4_BASE
+
 #endif				/* _IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-mx25/macro.h b/arch/arm/include/asm/arch-mx25/macro.h
new file mode 100644
index 0000000000..276c71ccd6
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx25/macro.h
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2011
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Common asm macros for imx25
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_MACRO_H__
+#define __ASM_ARM_ARCH_MACRO_H__
+#ifdef __ASSEMBLY__
+
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/asm-offsets.h>
+
+.macro init_aips
+	write32	IMX_AIPS1_BASE + AIPS_MPR_0_7, 0x77777777
+	write32	IMX_AIPS1_BASE + AIPS_MPR_8_15, 0x77777777
+	write32	IMX_AIPS2_BASE + AIPS_MPR_0_7, 0x77777777
+	write32	IMX_AIPS2_BASE + AIPS_MPR_8_15, 0x77777777
+.endm
+
+.macro init_max
+	write32	IMX_MAX_BASE + MAX_MPR0, 0x43210
+	write32	IMX_MAX_BASE + MAX_MPR1, 0x43210
+	write32	IMX_MAX_BASE + MAX_MPR2, 0x43210
+	write32	IMX_MAX_BASE + MAX_MPR3, 0x43210
+	write32	IMX_MAX_BASE + MAX_MPR4, 0x43210
+
+	write32	IMX_MAX_BASE + MAX_SGPCR0, 0x10
+	write32	IMX_MAX_BASE + MAX_SGPCR1, 0x10
+	write32	IMX_MAX_BASE + MAX_SGPCR2, 0x10
+	write32	IMX_MAX_BASE + MAX_SGPCR3, 0x10
+	write32	IMX_MAX_BASE + MAX_SGPCR4, 0x10
+
+	write32	IMX_MAX_BASE + MAX_MGPCR0, 0x0
+	write32	IMX_MAX_BASE + MAX_MGPCR1, 0x0
+	write32	IMX_MAX_BASE + MAX_MGPCR2, 0x0
+	write32	IMX_MAX_BASE + MAX_MGPCR3, 0x0
+	write32	IMX_MAX_BASE + MAX_MGPCR4, 0x0
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARM_ARCH_MACRO_H__ */
diff --git a/arch/arm/include/asm/arch-mx27/asm-offsets.h b/arch/arm/include/asm/arch-mx27/asm-offsets.h
deleted file mode 100644
index 497afe5745..0000000000
--- a/arch/arm/include/asm/arch-mx27/asm-offsets.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#define AIPI1_PSR0	0x10000000
-#define AIPI1_PSR1	0x10000004
-#define AIPI2_PSR0	0x10020000
-#define AIPI2_PSR1	0x10020004
-#define CSCR		0x10027000
-#define MPCTL0		0x10027004
-#define SPCTL0		0x1002700c
-#define PCDR0		0x10027018
-#define PCDR1		0x1002701c
-#define PCCR0		0x10027020
-#define PCCR1		0x10027024
-#define ESDCTL0_ROF	0x00
-#define ESDCFG0_ROF	0x04
-#define ESDCTL1_ROF	0x08
-#define ESDCFG1_ROF	0x0C
-#define ESDMISC_ROF	0x10
diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
index 8f40aa728c..b4b2fe61a6 100644
--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
@@ -29,7 +29,7 @@
 extern void imx_gpio_mode (int gpio_mode);
 
 #ifdef CONFIG_MXC_UART
-extern void mx27_uart_init_pins(void);
+extern void mx27_uart1_init_pins(void);
 #endif /* CONFIG_MXC_UART */
 
 #ifdef CONFIG_FEC_MXC
diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h
index 9f7ae8036e..fb035c4993 100644
--- a/arch/arm/include/asm/arch-mx31/clock.h
+++ b/arch/arm/include/asm/arch-mx31/clock.h
@@ -24,8 +24,15 @@
 #ifndef __ASM_ARCH_CLOCK_H
 #define __ASM_ARCH_CLOCK_H
 
-extern u32 mx31_get_ipg_clk(void);
-#define imx_get_uartclk mx31_get_ipg_clk
+enum mxc_clock {
+	MXC_ARM_CLK,
+	MXC_IPG_CLK,
+	MXC_CSPI_CLK,
+	MXC_UART_CLK,
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+extern u32 imx_get_uartclk();
 extern void mx31_gpio_mux(unsigned long mode);
 extern void mx31_set_pad(enum iomux_pins pin, u32 config);
 
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 306f966139..3c8d6076d2 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -746,7 +746,7 @@ enum iomux_pins {
 #define IRAM_SIZE	(16 * 1024)
 
 #define MX31_AIPS1_BASE_ADDR	0x43f00000
-#define MX31_OTG_BASE_ADDR	(MX31_AIPS1_BASE_ADDR + 0x88000)
+#define IMX_USB_BASE		(MX31_AIPS1_BASE_ADDR + 0x88000)
 
 /* USB portsc */
 /* values for portsc field */
diff --git a/arch/arm/include/asm/arch-mx5/asm-offsets.h b/arch/arm/include/asm/arch-mx5/asm-offsets.h
deleted file mode 100644
index 793f69c5e6..0000000000
--- a/arch/arm/include/asm/arch-mx5/asm-offsets.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * needed for arch/arm/cpu/armv7/mx51/lowlevel_init.S
- *
- * These should be auto-generated
- */
-/* CCM */
-#define CLKCTL_CCR              0x00
-#define CLKCTL_CCDR             0x04
-#define CLKCTL_CSR              0x08
-#define CLKCTL_CCSR             0x0C
-#define CLKCTL_CACRR            0x10
-#define CLKCTL_CBCDR            0x14
-#define CLKCTL_CBCMR            0x18
-#define CLKCTL_CSCMR1           0x1C
-#define CLKCTL_CSCMR2           0x20
-#define CLKCTL_CSCDR1           0x24
-#define CLKCTL_CS1CDR           0x28
-#define CLKCTL_CS2CDR           0x2C
-#define CLKCTL_CDCDR            0x30
-#define CLKCTL_CHSCCDR          0x34
-#define CLKCTL_CSCDR2           0x38
-#define CLKCTL_CSCDR3           0x3C
-#define CLKCTL_CSCDR4           0x40
-#define CLKCTL_CWDR             0x44
-#define CLKCTL_CDHIPR           0x48
-#define CLKCTL_CDCR             0x4C
-#define CLKCTL_CTOR             0x50
-#define CLKCTL_CLPCR            0x54
-#define CLKCTL_CISR             0x58
-#define CLKCTL_CIMR             0x5C
-#define CLKCTL_CCOSR            0x60
-#define CLKCTL_CGPR             0x64
-#define CLKCTL_CCGR0            0x68
-#define CLKCTL_CCGR1            0x6C
-#define CLKCTL_CCGR2            0x70
-#define CLKCTL_CCGR3            0x74
-#define CLKCTL_CCGR4            0x78
-#define CLKCTL_CCGR5            0x7C
-#define CLKCTL_CCGR6            0x80
-#if defined(CONFIG_MX53)
-#define CLKCTL_CCGR7            0x84
-#define CLKCTL_CMEOR            0x88
-#elif defined(CONFIG_MX51)
-#define CLKCTL_CMEOR            0x84
-#endif
-
-/* DPLL */
-#define PLL_DP_CTL	0x00
-#define PLL_DP_CONFIG	0x04
-#define PLL_DP_OP	0x08
-#define PLL_DP_MFD	0x0C
-#define PLL_DP_MFN	0x10
-#define PLL_DP_HFS_OP	0x1C
-#define PLL_DP_HFS_MFD	0x20
-#define PLL_DP_HFS_MFN	0x24
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 9589a62a12..e83ca29006 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -317,9 +317,27 @@ struct clkctl {
 	u32	ccgr4;
 	u32	ccgr5;
 	u32	ccgr6;
+#if defined(CONFIG_MX53)
+	u32	ccgr7;
+#endif
 	u32	cmeor;
 };
 
+/* DPLL registers */
+struct dpll {
+	u32	dp_ctl;
+	u32	dp_config;
+	u32	dp_op;
+	u32	dp_mfd;
+	u32	dp_mfn;
+	u32	dp_mfn_minus;
+	u32	dp_mfn_plus;
+	u32	dp_hfs_op;
+	u32	dp_hfs_mfd;
+	u32	dp_hfs_mfn;
+	u32	dp_mfn_togc;
+	u32	dp_destat;
+};
 /* WEIM registers */
 struct weim {
 	u32	cs0gcr1;
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index 270f163eee..879e20e024 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -106,6 +106,11 @@ static inline int test_bit(int nr, const void * addr)
     return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
 }
 
+static inline int __ilog2(unsigned int x)
+{
+	return generic_fls(x) - 1;
+}
+
 /*
  * ffz = Find First Zero in word. Undefined if no zero exists,
  * so code should check against ~0UL first..
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index fc52a26b79..6bbedf45dd 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -281,6 +281,10 @@ void board_init_f (ulong bootflag)
 
 	gd->mon_len = _bss_end_ofs;
 
+#ifdef CONFIG_MACH_TYPE
+	gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
+#endif
+
 	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
 		if ((*init_fnc_ptr)() != 0) {
 			hang ();