Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

8 files changed, 147 insertions, 80 deletions

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 49ea6cc752..f5b39c067c 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -299,6 +299,16 @@ void mpc85xx_reginfo(void)
 
 /* Common ddr init for non-corenet fsl 85xx platforms */
 #ifndef CONFIG_FSL_CORENET
+#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR)
+phys_size_t initdram(int board_type)
+{
+#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
+	return fsl_ddr_sdram_size();
+#else
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+#endif
+}
+#else /* CONFIG_SYS_RAMBOOT */
 phys_size_t initdram(int board_type)
 {
 	phys_size_t dram_size = 0;
@@ -348,6 +358,7 @@ phys_size_t initdram(int board_type)
 	puts("DDR: ");
 	return dram_size;
 }
+#endif /* CONFIG_SYS_RAMBOOT */
 #endif
 
 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 5642cd7b05..6f256cf7a7 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -145,6 +145,22 @@ static void enable_cpc(void)
 	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 		u32 cpccfg0 = in_be32(&cpc->cpccfg0);
 		size += CPC_CFG0_SZ_K(cpccfg0);
+#ifdef CONFIG_RAMBOOT_PBL
+		if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
+			/* find and disable LAW of SRAM */
+			struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
+
+			if (law.index == -1) {
+				printf("\nFatal error happened\n");
+				return;
+			}
+			disable_law(law.index);
+
+			clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
+			out_be32(&cpc->cpccsr0, 0);
+			out_be32(&cpc->cpcsrcr0, 0);
+		}
+#endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
 		setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
@@ -168,6 +184,9 @@ void invalidate_cpc(void)
 	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 
 	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
+		/* skip CPC when it used as all SRAM */
+		if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
+			continue;
 		/* Flash invalidate the CPC and clear all the locks */
 		out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
 		while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
index 8fb27abc55..796d398426 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
@@ -33,17 +33,15 @@ void cpu_init_f(void)
 	 */
 	out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
 
-#if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM)
-	set_lbc_br(0, CONFIG_NAND_BR_PRELIM);
-	set_lbc_or(0, CONFIG_NAND_OR_PRELIM);
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
 #else
-#error  CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
+#error  CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM must be defined
 #endif
 
 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
 	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
-	char *l2srbar;
-	int i;
 
 	out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
 
@@ -54,10 +52,5 @@ void cpu_init_f(void)
 	/* set L2E=1 & L2SRAM=001 */
 	out_be32(&l2cache->l2ctl,
 		(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
-
-	/* Initialize L2 SRAM to zero */
-	l2srbar = (char *)CONFIG_SYS_INIT_L2_ADDR;
-	for (i = 0; i < CONFIG_SYS_L2_SIZE; i++)
-		l2srbar[i] = 0;
 #endif
 }
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 7fc00d8c6f..f58d6d617c 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -109,10 +109,13 @@ int serdes_lane_enabled(int lane)
 		return 0;
 
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
-	if (!IS_SVR_REV(get_svr(), 1, 0))
-		if (bank > 0)
-			return !(srds_lpd_b[bank] &
-					(8 >> (lane - (6 + 4 * bank))));
+	/*
+	 * For banks two and three, use the srds_lpd_b[] array instead of the
+	 * RCW, because this array contains the real values of SRDS_LPD_B2 and
+	 * SRDS_LPD_B3.
+	 */
+	if (bank > 0)
+		return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank))));
 #endif
 
 	return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit));
@@ -303,15 +306,19 @@ void fsl_serdes_init(void)
 	}
 
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
-	if (!IS_SVR_REV(get_svr(), 1, 0))
-		for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) {
-			sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1);
-			srds_lpd_arg = hwconfig_subarg_f("serdes", srds_lpd_opt,
-						       &arglen, buf);
-			if (srds_lpd_arg)
-				srds_lpd_b[bank] = simple_strtoul(srds_lpd_arg,
-								  NULL, 0);
-		}
+	/*
+	 * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3
+	 * hwconfig options into the srds_lpd_b[] array.  See README.p4080ds
+	 * for a description of these options.
+	 */
+	for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) {
+		sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1);
+		srds_lpd_arg =
+			hwconfig_subarg_f("serdes", srds_lpd_opt, &arglen, buf);
+		if (srds_lpd_arg)
+			srds_lpd_b[bank] =
+				simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf;
+	}
 #endif
 
 	/* Look for banks with all lanes disabled, and power down the bank. */
@@ -324,32 +331,12 @@ void fsl_serdes_init(void)
 	}
 
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
-	if (IS_SVR_REV(get_svr(), 1, 0)) {
-		/* At least one bank must be disabled due to SERDES8.  If
-		 * no bank is found to be disabled based on lane
-		 * disables, disable bank 3 because we can't turn off its
-		 * lanes in the RCW without disabling MDIO due to erratum
-		 * GEN8.
-		 *
-		 * This means that if you are relying on bank 3 being
-		 * disabled to avoid SERDES8, in some cases you cannot
-		 * also disable all lanes of another bank, or else bank
-		 * 3 won't be disabled, leaving you with a configuration
-		 * that isn't valid according to SERDES8 (e.g. if banks
-		 * 2 and 3 have the same clock, and bank 1 is disabled
-		 * instead of 3).
-		 */
-		for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
-			if (!have_bank[bank])
-				break;
-		}
-
-		if (bank == SRDS_MAX_BANK)
-			have_bank[FSL_SRDS_BANK_3] = 0;
-	} else {
-		if (have_bank[FSL_SRDS_BANK_2])
-			have_bank[FSL_SRDS_BANK_3] = 1;
-	}
+	/*
+	 * Bank two uses the clock from bank three, so if bank two is enabled,
+	 * then bank three must also be enabled.
+	 */
+	if (have_bank[FSL_SRDS_BANK_2])
+		have_bank[FSL_SRDS_BANK_3] = 1;
 #endif
 
 	for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
@@ -455,19 +442,16 @@ void fsl_serdes_init(void)
 		bank = idx;
 
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
-		if (!IS_SVR_REV(get_svr(), 1, 0)) {
-			/*
-			 * Change bank init order to 0, 2, 1, so that the
-			 * third bank's PLL is established before we
-			 * start the second bank which shares the third
-			 * bank's PLL.
-			 */
+		/*
+		 * Change bank init order to 0, 2, 1, so that the third bank's
+		 * PLL is established before we start the second bank.  The
+		 * second bank uses the third bank's PLL.
+		 */
 
-			if (idx == 1)
-				bank = FSL_SRDS_BANK_3;
-			else if (idx == 2)
-				bank = FSL_SRDS_BANK_2;
-		}
+		if (idx == 1)
+			bank = FSL_SRDS_BANK_3;
+		else if (idx == 2)
+			bank = FSL_SRDS_BANK_2;
 #endif
 
 		/* Skip disabled banks */
@@ -475,14 +459,18 @@ void fsl_serdes_init(void)
 			continue;
 
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
-		if (!IS_SVR_REV(get_svr(), 1, 0)) {
-			if (idx == 1) {
-				p4080_erratum_serdes8(srds_regs, gur,
-						      serdes8_devdisr,
-						      serdes8_devdisr2, cfg);
-			} else if (idx == 2) {
-				enable_bank(gur, FSL_SRDS_BANK_2);
-			}
+		if (idx == 1) {
+			/*
+			 * Re-enable devices on banks two and three that were
+			 * disabled by the RCW, and then enable bank three. The
+			 * devices need to be enabled before either bank is
+			 * powered up.
+			 */
+			p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr,
+					      serdes8_devdisr2, cfg);
+		} else if (idx == 2) {
+			/* Eable bank two now that bank three is enabled. */
+			enable_bank(gur, FSL_SRDS_BANK_2);
 		}
 #endif
 
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index e530494102..c4c156d737 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -28,6 +28,7 @@
 
 #include <common.h>
 #include <ppc_asm.tmpl>
+#include <linux/compiler.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 
@@ -156,7 +157,7 @@ void get_sys_info (sys_info_t * sysInfo)
 #endif
 	int i;
 #ifdef CONFIG_QE
-	u32 qe_ratio;
+	__maybe_unused u32 qe_ratio;
 #endif
 
 	plat_ratio = (gur->porpllsr) & 0x0000003e;
@@ -184,10 +185,15 @@ void get_sys_info (sys_info_t * sysInfo)
 #endif
 
 #ifdef CONFIG_QE
+#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+    defined(CONFIG_P1021) || defined(CONFIG_P1025)
+	sysInfo->freqQE =  sysInfo->freqSystemBus;
+#else
 	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
 			>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
 	sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
 #endif
+#endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 		sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 4228161c62..41fd86c4e2 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -88,6 +88,7 @@
 
 #elif defined(CONFIG_P1010)
 #define CONFIG_MAX_CPUS			1
+#define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
@@ -115,6 +116,9 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define QE_MURAM_SIZE			0x6000UL
+#define MAX_QE_RISC			1
+#define QE_NUM_OF_SNUM			28
 
 /* P1013 is single core version of P1022 */
 #elif defined(CONFIG_P1013)
@@ -128,6 +132,7 @@
 
 #elif defined(CONFIG_P1014)
 #define CONFIG_MAX_CPUS			1
+#define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
@@ -155,6 +160,9 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define QE_MURAM_SIZE			0x6000UL
+#define MAX_QE_RISC			1
+#define QE_NUM_OF_SNUM			28
 
 /* P1017 is single core version of P1023 */
 #elif defined(CONFIG_P1017)
@@ -185,6 +193,9 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define QE_MURAM_SIZE			0x6000UL
+#define MAX_QE_RISC			1
+#define QE_NUM_OF_SNUM			28
 
 #elif defined(CONFIG_P1022)
 #define CONFIG_MAX_CPUS			2
@@ -225,6 +236,9 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define QE_MURAM_SIZE			0x6000UL
+#define MAX_QE_RISC			1
+#define QE_NUM_OF_SNUM			28
 
 /* P2010 is single core version of P2020 */
 #elif defined(CONFIG_P2010)
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index 99dddb4f00..127a84039c 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -271,6 +271,7 @@ typedef struct memctl_options_s {
 } memctl_options_t;
 
 extern phys_size_t fsl_ddr_sdram(void);
+extern phys_size_t fsl_ddr_sdram_size(void);
 extern int fsl_use_spd(void);
 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 					unsigned int ctrl_num);
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index d26d648b13..b51017b550 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1923,7 +1923,31 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR_SD_DATA		0x80000000
 #define MPC85xx_PMUXCR_SDHC_CD		0x40000000
 #define MPC85xx_PMUXCR_SDHC_WP		0x20000000
+#define MPC85xx_PMUXCR_TDM_ENA		0x00800000
+#define MPC85xx_PMUXCR_QE0		0x00008000
+#define MPC85xx_PMUXCR_QE1		0x00004000
+#define MPC85xx_PMUXCR_QE2		0x00002000
+#define MPC85xx_PMUXCR_QE3		0x00001000
+#define MPC85xx_PMUXCR_QE4		0x00000800
+#define MPC85xx_PMUXCR_QE5		0x00000400
+#define MPC85xx_PMUXCR_QE6		0x00000200
+#define MPC85xx_PMUXCR_QE7		0x00000100
+#define MPC85xx_PMUXCR_QE8		0x00000080
+#define MPC85xx_PMUXCR_QE9		0x00000040
+#define MPC85xx_PMUXCR_QE10		0x00000020
+#define MPC85xx_PMUXCR_QE11		0x00000010
+#define MPC85xx_PMUXCR_QE12		0x00000008
+#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
+#define MPC85xx_PMUXCR_TDM_MASK		0x0001cc00
+#define MPC85xx_PMUXCR_TDM		0x00014800
+#define MPC85xx_PMUXCR_SPI_MASK		0x00600000
+#define MPC85xx_PMUXCR_SPI		0x00000000
+#endif
 	u32	pmuxcr2;	/* Alt. function signal multiplex control 2 */
+#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
+#define MPC85xx_PMUXCR2_ETSECUSB_MASK	0x001f1000
+#define MPC85xx_PMUXCR2_USB		0x00150000
+#endif
 	u8	res6[8];
 	u32	devdisr;	/* Device disable control */
 #define MPC85xx_DEVDISR_PCI1		0x80000000
@@ -1956,32 +1980,43 @@ typedef struct ccsr_gur {
 	u8	res9[12];
 	u32	pvr;		/* Processor version */
 	u32	svr;		/* System version */
-	u8	res10a[8];
+	u8	res10[8];
 	u32	rstcr;		/* Reset control */
 #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
-	u8	res10b[76];
+	u8	res11a[76];
 	par_io_t qe_par_io[7];
-	u8	res10c[1600];
+	u8	res11b[1600];
+#elif defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+      defined(CONFIG_P1021) || defined(CONFIG_P1025)
+	u8      res11a[12];
+	u32     iovselsr;
+	u8      res11b[60];
+	par_io_t qe_par_io[3];
+	u8      res11c[1496];
 #else
-	u8	res10b[1868];
+	u8	res11a[1868];
 #endif
 	u32	clkdvdr;	/* Clock Divide register */
-	u8	res10d[1532];
+	u8	res12[1532];
 	u32	clkocr;		/* Clock out select */
-	u8	res11[12];
+	u8	res13[12];
 	u32	ddrdllcr;	/* DDR DLL control */
-	u8	res12[12];
+	u8	res14[12];
 	u32	lbcdllcr;	/* LBC DLL control */
-	u8	res13[248];
+	u8	res15[248];
 	u32	lbiuiplldcr0;	/* LBIU PLL Debug Reg 0 */
 	u32	lbiuiplldcr1;	/* LBIU PLL Debug Reg 1 */
 	u32	ddrioovcr;	/* DDR IO Override Control */
 	u32	tsec12ioovcr;	/* eTSEC 1/2 IO override control */
 	u32	tsec34ioovcr;	/* eTSEC 3/4 IO override control */
-	u8	res15[61648];
+	u8      res16[52];
+	u32	sdhcdcr;	/* SDHC debug control register */
+	u8      res17[61592];
 } ccsr_gur_t;
 #endif
 
+#define SDHCDCR_CD_INV		0x80000000 /* invert SDHC card detect */
+
 typedef struct serdes_corenet {
 	struct {
 		u32	rstctl;	/* Reset Control Register */