Merge branch 'master' of git://git.denx.de/u-boot-arm

65 files changed, 142 insertions, 2216 deletions

diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index cfa42094ca..98c1253f4a 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -18,7 +18,8 @@ endif
 LDFLAGS_FINAL += --gc-sections
 PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
 		     -fno-common -ffixed-r9
-PLATFORM_RELFLAGS += $(call cc-option, -msoft-float)
+PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
+      $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
 
 # Support generic board on ARM
 __HAVE_ARCH_GENERIC_BOARD := y
diff --git a/arch/arm/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk
index b4d396de84..f74228cdba 100644
--- a/arch/arm/cpu/arm1136/config.mk
+++ b/arch/arm/cpu/arm1136/config.mk
@@ -7,13 +7,6 @@
 
 # Make ARMv5 to allow more compilers to work, even though its v6.
 PLATFORM_CPPFLAGS += -march=armv5
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
 
 ifneq ($(CONFIG_IMX_CONFIG),)
 ifdef CONFIG_SPL
diff --git a/arch/arm/cpu/arm1176/bcm2835/mbox.c b/arch/arm/cpu/arm1176/bcm2835/mbox.c
index 4daf1e410c..3b17a31eac 100644
--- a/arch/arm/cpu/arm1176/bcm2835/mbox.c
+++ b/arch/arm/cpu/arm1176/bcm2835/mbox.c
@@ -8,7 +8,7 @@
 #include <asm/io.h>
 #include <asm/arch/mbox.h>
 
-#define TIMEOUT (100 * 1000) /* 100mS in uS */
+#define TIMEOUT 1000 /* ms */
 
 int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv)
 {
diff --git a/arch/arm/cpu/arm1176/bcm2835/timer.c b/arch/arm/cpu/arm1176/bcm2835/timer.c
index 2edd6711da..017907cfb8 100644
--- a/arch/arm/cpu/arm1176/bcm2835/timer.c
+++ b/arch/arm/cpu/arm1176/bcm2835/timer.c
@@ -18,11 +18,6 @@
 #include <asm/io.h>
 #include <asm/arch/timer.h>
 
-int timer_init(void)
-{
-	return 0;
-}
-
 ulong get_timer_us(ulong base)
 {
 	struct bcm2835_timer_regs *regs =
diff --git a/arch/arm/cpu/arm1176/config.mk b/arch/arm/cpu/arm1176/config.mk
index f4631cb777..5dc2ebb27b 100644
--- a/arch/arm/cpu/arm1176/config.mk
+++ b/arch/arm/cpu/arm1176/config.mk
@@ -7,11 +7,3 @@
 
 # Make ARMv5 to allow more compilers to work, even though its v6.
 PLATFORM_CPPFLAGS += -march=armv5t
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\
-			$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/arm720t/config.mk b/arch/arm/cpu/arm720t/config.mk
index 2581f0ae67..772fb413e8 100644
--- a/arch/arm/cpu/arm720t/config.mk
+++ b/arch/arm/cpu/arm720t/config.mk
@@ -7,11 +7,3 @@
 #
 
 PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\
-			$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/arm920t/config.mk b/arch/arm/cpu/arm920t/config.mk
index 67537dcedc..799afff028 100644
--- a/arch/arm/cpu/arm920t/config.mk
+++ b/arch/arm/cpu/arm920t/config.mk
@@ -6,10 +6,3 @@
 #
 
 PLATFORM_CPPFLAGS += -march=armv4
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk
index 12b0d09d37..4d9895f5d8 100644
--- a/arch/arm/cpu/arm926ejs/config.mk
+++ b/arch/arm/cpu/arm926ejs/config.mk
@@ -6,13 +6,6 @@
 #
 
 PLATFORM_CPPFLAGS += -march=armv5te
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
 
 ifneq ($(CONFIG_IMX_CONFIG),)
 ifdef CONFIG_SPL
diff --git a/arch/arm/cpu/arm946es/config.mk b/arch/arm/cpu/arm946es/config.mk
index eb81a5708d..438668d6ff 100644
--- a/arch/arm/cpu/arm946es/config.mk
+++ b/arch/arm/cpu/arm946es/config.mk
@@ -6,10 +6,3 @@
 #
 
 PLATFORM_CPPFLAGS +=  -march=armv4
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/arm_intcm/config.mk b/arch/arm/cpu/arm_intcm/config.mk
index eb81a5708d..438668d6ff 100644
--- a/arch/arm/cpu/arm_intcm/config.mk
+++ b/arch/arm/cpu/arm_intcm/config.mk
@@ -6,10 +6,3 @@
 #
 
 PLATFORM_CPPFLAGS +=  -march=armv4
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk
index f0d9c04327..38b7c401f8 100644
--- a/arch/arm/cpu/armv7/config.mk
+++ b/arch/arm/cpu/armv7/config.mk
@@ -10,14 +10,6 @@
 PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5)
 PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7)
 
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
-
 # SEE README.arm-unaligned-accesses
 PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
 PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index dfa3760dfc..8e7411d437 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -418,55 +418,6 @@ static void setup_dplls(void)
 #endif
 }
 
-#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
-static void setup_non_essential_dplls(void)
-{
-	u32 abe_ref_clk;
-	const struct dpll_params *params;
-
-	/* IVA */
-	clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva,
-		CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
-
-	params = get_iva_dpll_params(*dplls_data);
-	do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
-
-	/* Configure ABE dpll */
-	params = get_abe_dpll_params(*dplls_data);
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
-	abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
-
-	if (omap_revision() == DRA752_ES1_0)
-		/* Select the sys clk for dpll_abe */
-		clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel,
-				CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK,
-				CM_ABE_PLL_SYS_CLKSEL_SYSCLK2);
-#else
-	abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
-	/*
-	 * We need to enable some additional options to achieve
-	 * 196.608MHz from 32768 Hz
-	 */
-	setbits_le32((*prcm)->cm_clkmode_dpll_abe,
-			CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
-			CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
-			CM_CLKMODE_DPLL_LPMODE_EN_MASK|
-			CM_CLKMODE_DPLL_REGM4XEN_MASK);
-	/* Spend 4 REFCLK cycles at each stage */
-	clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe,
-			CM_CLKMODE_DPLL_RAMP_RATE_MASK,
-			1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
-#endif
-
-	/* Select the right reference clk */
-	clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel,
-			CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
-			abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
-	/* Lock the dpll */
-	do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
-}
-#endif
-
 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
 {
 	u32 offset_code;
@@ -760,10 +711,6 @@ void prcm_init(void)
 		timer_init();
 		scale_vcores(*omap_vcores);
 		setup_dplls();
-#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
-		setup_non_essential_dplls();
-		enable_non_essential_clocks();
-#endif
 		setup_warmreset_time();
 		break;
 	default:
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index cd6289b4fc..429c4becf3 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -179,8 +179,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
 	writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
 	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 
-	if ((omap_revision() >= OMAP5430_ES1_0) ||
-				(omap_revision() == DRA752_ES1_0)) {
+	if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) {
 		writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
 			&emif->emif_l3_config);
 	} else if (omap_revision() >= OMAP4460_ES1_0) {
@@ -309,7 +308,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
 	 * The same sequence should work on OMAP5432 as well. But strange that
 	 * it is not working
 	 */
-	if (omap_revision() == DRA752_ES1_0) {
+	if (is_dra7xx()) {
 		do_ext_phy_settings(base, regs);
 		writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 		writel(regs->sdram_config_init, &emif->emif_sdram_config);
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 85d375432f..bf2951031d 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -43,16 +43,10 @@ static void set_mux_conf_regs(void)
 		set_muxconf_regs_essential();
 		break;
 	case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
-#ifdef CONFIG_SYS_ENABLE_PADS_ALL
-		set_muxconf_regs_non_essential();
-#endif
 		break;
 	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
 	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
 		set_muxconf_regs_essential();
-#ifdef CONFIG_SYS_ENABLE_PADS_ALL
-		set_muxconf_regs_non_essential();
-#endif
 		break;
 	}
 }
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
index 1b2f439241..4dec73e9ec 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -399,91 +399,6 @@ void enable_basic_uboot_clocks(void)
 			 1);
 }
 
-/*
- * Enable non-essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_non_essential_clocks(void)
-{
-	u32 const clk_domains_non_essential[] = {
-		(*prcm)->cm_mpu_m3_clkstctrl,
-		(*prcm)->cm_ivahd_clkstctrl,
-		(*prcm)->cm_dsp_clkstctrl,
-		(*prcm)->cm_dss_clkstctrl,
-		(*prcm)->cm_sgx_clkstctrl,
-		(*prcm)->cm1_abe_clkstctrl,
-		(*prcm)->cm_c2c_clkstctrl,
-		(*prcm)->cm_cam_clkstctrl,
-		(*prcm)->cm_dss_clkstctrl,
-		(*prcm)->cm_sdma_clkstctrl,
-		0
-	};
-
-	u32 const clk_modules_hw_auto_non_essential[] = {
-		(*prcm)->cm_l3instr_l3_3_clkctrl,
-		(*prcm)->cm_l3instr_l3_instr_clkctrl,
-		(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
-		(*prcm)->cm_l3init_hsi_clkctrl,
-		0
-	};
-
-	u32 const clk_modules_explicit_en_non_essential[] = {
-		(*prcm)->cm1_abe_aess_clkctrl,
-		(*prcm)->cm1_abe_pdm_clkctrl,
-		(*prcm)->cm1_abe_dmic_clkctrl,
-		(*prcm)->cm1_abe_mcasp_clkctrl,
-		(*prcm)->cm1_abe_mcbsp1_clkctrl,
-		(*prcm)->cm1_abe_mcbsp2_clkctrl,
-		(*prcm)->cm1_abe_mcbsp3_clkctrl,
-		(*prcm)->cm1_abe_slimbus_clkctrl,
-		(*prcm)->cm1_abe_timer5_clkctrl,
-		(*prcm)->cm1_abe_timer6_clkctrl,
-		(*prcm)->cm1_abe_timer7_clkctrl,
-		(*prcm)->cm1_abe_timer8_clkctrl,
-		(*prcm)->cm1_abe_wdt3_clkctrl,
-		(*prcm)->cm_l4per_gptimer9_clkctrl,
-		(*prcm)->cm_l4per_gptimer10_clkctrl,
-		(*prcm)->cm_l4per_gptimer11_clkctrl,
-		(*prcm)->cm_l4per_gptimer3_clkctrl,
-		(*prcm)->cm_l4per_gptimer4_clkctrl,
-		(*prcm)->cm_l4per_hdq1w_clkctrl,
-		(*prcm)->cm_l4per_mcbsp4_clkctrl,
-		(*prcm)->cm_l4per_mcspi2_clkctrl,
-		(*prcm)->cm_l4per_mcspi3_clkctrl,
-		(*prcm)->cm_l4per_mcspi4_clkctrl,
-		(*prcm)->cm_l4per_mmcsd3_clkctrl,
-		(*prcm)->cm_l4per_mmcsd4_clkctrl,
-		(*prcm)->cm_l4per_mmcsd5_clkctrl,
-		(*prcm)->cm_l4per_uart1_clkctrl,
-		(*prcm)->cm_l4per_uart2_clkctrl,
-		(*prcm)->cm_l4per_uart4_clkctrl,
-		(*prcm)->cm_wkup_keyboard_clkctrl,
-		(*prcm)->cm_wkup_wdtimer2_clkctrl,
-		(*prcm)->cm_cam_iss_clkctrl,
-		(*prcm)->cm_cam_fdif_clkctrl,
-		(*prcm)->cm_dss_dss_clkctrl,
-		(*prcm)->cm_sgx_sgx_clkctrl,
-		0
-	};
-
-	/* Enable optional functional clock for ISS */
-	setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
-
-	/* Enable all optional functional clocks of DSS */
-	setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
-
-	do_enable_clocks(clk_domains_non_essential,
-			 clk_modules_hw_auto_non_essential,
-			 clk_modules_explicit_en_non_essential,
-			 0);
-
-	/* Put camera module in no sleep mode */
-	clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
-			MODULE_CLKCTRL_MODULEMODE_MASK,
-			CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
-			MODULE_CLKCTRL_MODULEMODE_SHIFT);
-}
-
 void hw_data_init(void)
 {
 	u32 omap_rev = omap_revision();
diff --git a/arch/arm/cpu/armv7/omap5/abb.c b/arch/arm/cpu/armv7/omap5/abb.c
index 31b679516f..3bf88979e5 100644
--- a/arch/arm/cpu/armv7/omap5/abb.c
+++ b/arch/arm/cpu/armv7/omap5/abb.c
@@ -28,18 +28,25 @@
 s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
 {
 	u32 vset;
+	u32 fuse_enable_mask = OMAP5_ABB_FUSE_ENABLE_MASK;
+	u32 fuse_vset_mask = OMAP5_ABB_FUSE_VSET_MASK;
 
+	if (!is_omap54xx()) {
+		/* DRA7 */
+		fuse_enable_mask = DRA7_ABB_FUSE_ENABLE_MASK;
+		fuse_vset_mask = DRA7_ABB_FUSE_VSET_MASK;
+	}
 	/*
 	 * ABB parameters must be properly fused
 	 * otherwise ABB should be disabled
 	 */
 	vset = readl(fuse);
-	if (!(vset & OMAP5_ABB_FUSE_ENABLE_MASK))
+	if (!(vset & fuse_enable_mask))
 		return -1;
 
 	/* prepare VSET value for LDOVBB mux register */
-	vset &= OMAP5_ABB_FUSE_VSET_MASK;
-	vset >>= ffs(OMAP5_ABB_FUSE_VSET_MASK) - 1;
+	vset &= fuse_vset_mask;
+	vset >>= ffs(fuse_vset_mask) - 1;
 	vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1;
 	vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK;
 
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 5268a1fca5..ad971327bf 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -486,94 +486,6 @@ void enable_basic_uboot_clocks(void)
 			 1);
 }
 
-/*
- * Enable non-essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_non_essential_clocks(void)
-{
-	u32 const clk_domains_non_essential[] = {
-		(*prcm)->cm_mpu_m3_clkstctrl,
-		(*prcm)->cm_ivahd_clkstctrl,
-		(*prcm)->cm_dsp_clkstctrl,
-		(*prcm)->cm_dss_clkstctrl,
-		(*prcm)->cm_sgx_clkstctrl,
-		(*prcm)->cm1_abe_clkstctrl,
-		(*prcm)->cm_c2c_clkstctrl,
-		(*prcm)->cm_cam_clkstctrl,
-		(*prcm)->cm_dss_clkstctrl,
-		(*prcm)->cm_sdma_clkstctrl,
-		0
-	};
-
-	u32 const clk_modules_hw_auto_non_essential[] = {
-		(*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
-		(*prcm)->cm_ivahd_ivahd_clkctrl,
-		(*prcm)->cm_ivahd_sl2_clkctrl,
-		(*prcm)->cm_dsp_dsp_clkctrl,
-		(*prcm)->cm_l3instr_l3_3_clkctrl,
-		(*prcm)->cm_l3instr_l3_instr_clkctrl,
-		(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
-		(*prcm)->cm_l3init_hsi_clkctrl,
-		(*prcm)->cm_l4per_hdq1w_clkctrl,
-		0
-	};
-
-	u32 const clk_modules_explicit_en_non_essential[] = {
-		(*prcm)->cm1_abe_aess_clkctrl,
-		(*prcm)->cm1_abe_pdm_clkctrl,
-		(*prcm)->cm1_abe_dmic_clkctrl,
-		(*prcm)->cm1_abe_mcasp_clkctrl,
-		(*prcm)->cm1_abe_mcbsp1_clkctrl,
-		(*prcm)->cm1_abe_mcbsp2_clkctrl,
-		(*prcm)->cm1_abe_mcbsp3_clkctrl,
-		(*prcm)->cm1_abe_slimbus_clkctrl,
-		(*prcm)->cm1_abe_timer5_clkctrl,
-		(*prcm)->cm1_abe_timer6_clkctrl,
-		(*prcm)->cm1_abe_timer7_clkctrl,
-		(*prcm)->cm1_abe_timer8_clkctrl,
-		(*prcm)->cm1_abe_wdt3_clkctrl,
-		(*prcm)->cm_l4per_gptimer9_clkctrl,
-		(*prcm)->cm_l4per_gptimer10_clkctrl,
-		(*prcm)->cm_l4per_gptimer11_clkctrl,
-		(*prcm)->cm_l4per_gptimer3_clkctrl,
-		(*prcm)->cm_l4per_gptimer4_clkctrl,
-		(*prcm)->cm_l4per_mcspi2_clkctrl,
-		(*prcm)->cm_l4per_mcspi3_clkctrl,
-		(*prcm)->cm_l4per_mcspi4_clkctrl,
-		(*prcm)->cm_l4per_mmcsd3_clkctrl,
-		(*prcm)->cm_l4per_mmcsd4_clkctrl,
-		(*prcm)->cm_l4per_mmcsd5_clkctrl,
-		(*prcm)->cm_l4per_uart1_clkctrl,
-		(*prcm)->cm_l4per_uart2_clkctrl,
-		(*prcm)->cm_l4per_uart4_clkctrl,
-		(*prcm)->cm_wkup_keyboard_clkctrl,
-		(*prcm)->cm_wkup_wdtimer2_clkctrl,
-		(*prcm)->cm_cam_iss_clkctrl,
-		(*prcm)->cm_cam_fdif_clkctrl,
-		(*prcm)->cm_dss_dss_clkctrl,
-		(*prcm)->cm_sgx_sgx_clkctrl,
-		0
-	};
-
-	/* Enable optional functional clock for ISS */
-	setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
-
-	/* Enable all optional functional clocks of DSS */
-	setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
-
-	do_enable_clocks(clk_domains_non_essential,
-			 clk_modules_hw_auto_non_essential,
-			 clk_modules_explicit_en_non_essential,
-			 0);
-
-	/* Put camera module in no sleep mode */
-	clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
-			MODULE_CLKCTRL_MODULEMODE_MASK,
-			CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
-			MODULE_CLKCTRL_MODULEMODE_SHIFT);
-}
-
 const struct ctrl_ioregs ioregs_omap5430 = {
 	.ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
 	.ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
@@ -639,6 +551,7 @@ void hw_data_init(void)
 	break;
 
 	case DRA752_ES1_0:
+	case DRA752_ES1_1:
 	*prcm = &dra7xx_prcm;
 	*dplls_data = &dra7xx_dplls;
 	*omap_vcores = &dra752_volts;
@@ -666,6 +579,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)
 		*regs = &ioregs_omap5432_es2;
 		break;
 	case DRA752_ES1_0:
+	case DRA752_ES1_1:
 		*regs = &ioregs_dra7xx_es1;
 		break;
 
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index 5386ae0568..737d23ccb4 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -333,6 +333,9 @@ void init_omap_revision(void)
 	case DRA752_CONTROL_ID_CODE_ES1_0:
 		*omap_si_rev = DRA752_ES1_0;
 		break;
+	case DRA752_CONTROL_ID_CODE_ES1_1:
+		*omap_si_rev = DRA752_ES1_1;
+		break;
 	default:
 		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 	}
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 77c428b535..ff328070f7 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -432,11 +432,13 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
 	.control_srcomp_code_latch		= 0x4A002E84,
 	.control_ddr_control_ext_0		= 0x4A002E88,
 	.control_padconf_core_base		= 0x4A003400,
+	.control_std_fuse_opp_vdd_mpu_2		= 0x4A003B24,
 	.control_port_emif1_sdram_config	= 0x4AE0C110,
 	.control_port_emif1_lpddr2_nvm_config	= 0x4AE0C114,
 	.control_port_emif2_sdram_config	= 0x4AE0C118,
 	.control_emif1_sdram_config_ext		= 0x4AE0C144,
 	.control_emif2_sdram_config_ext		= 0x4AE0C148,
+	.control_wkup_ldovbb_mpu_voltage_ctrl	= 0x4AE0C158,
 	.control_padconf_mode			= 0x4AE0C5A0,
 	.control_xtal_oscillator		= 0x4AE0C5A4,
 	.control_i2c_2				= 0x4AE0C5A8,
@@ -807,6 +809,9 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_dsp_clkstctrl			= 0x4a005400,
 	.cm_dsp_dsp_clkctrl			= 0x4a005420,
 
+	/* prm irqstatus regs */
+	.prm_irqstatus_mpu_2			= 0x4ae06014,
+
 	/* cm2.ckgen */
 	.cm_clksel_usb_60mhz			= 0x4a008104,
 	.cm_clkmode_dpll_per			= 0x4a008140,
@@ -967,4 +972,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.prm_vc_val_bypass			= 0x4ae07da0,
 	.prm_vc_cfg_i2c_mode			= 0x4ae07db4,
 	.prm_vc_cfg_i2c_clk			= 0x4ae07db8,
+
+	.prm_abbldo_mpu_setup			= 0x4AE07DDC,
+	.prm_abbldo_mpu_ctrl			= 0x4AE07DE0,
 };
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 2e1870609a..16a91f911a 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -245,6 +245,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 		*regs = &emif_regs_ddr3_532_mhz_1cs_es2;
 		break;
 	case DRA752_ES1_0:
+	case DRA752_ES1_1:
 		switch (emif_nr) {
 		case 1:
 			*regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
@@ -273,6 +274,7 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 		*dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
 		break;
 	case DRA752_ES1_0:
+	case DRA752_ES1_1:
 	default:
 		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
 	}
@@ -460,6 +462,7 @@ static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
 		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 		break;
 	case DRA752_ES1_0:
+	case DRA752_ES1_1:
 		if (emif_nr == 1) {
 			*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
 			*size =
@@ -626,6 +629,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)
 			     sizeof(omap5_bug_00339_regs[0]);
 		break;
 	case DRA752_ES1_0:
+	case DRA752_ES1_1:
 		bug_00339_regs_ptr = dra_bug_00339_regs;
 		*iterations = sizeof(dra_bug_00339_regs)/
 			     sizeof(dra_bug_00339_regs[0]);
diff --git a/arch/arm/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk
index fd47c60939..894861fb4f 100644
--- a/arch/arm/cpu/ixp/config.mk
+++ b/arch/arm/cpu/ixp/config.mk
@@ -14,11 +14,3 @@ PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
 
 PLATFORM_LDFLAGS += -EB
 USE_PRIVATE_LIBGCC = yes
-
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/pxa/config.mk b/arch/arm/cpu/pxa/config.mk
index f2befbe515..986b11b419 100644
--- a/arch/arm/cpu/pxa/config.mk
+++ b/arch/arm/cpu/pxa/config.mk
@@ -7,13 +7,6 @@
 #
 
 PLATFORM_CPPFLAGS += -mcpu=xscale
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# ========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
 
 #
 # !WARNING!
diff --git a/arch/arm/cpu/sa1100/config.mk b/arch/arm/cpu/sa1100/config.mk
index b3026cc50d..3afa685b3f 100644
--- a/arch/arm/cpu/sa1100/config.mk
+++ b/arch/arm/cpu/sa1100/config.mk
@@ -7,10 +7,3 @@
 #
 
 PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# ========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/sa1100/timer.c b/arch/arm/cpu/sa1100/timer.c
index 4b981e46e7..0a0006b426 100644
--- a/arch/arm/cpu/sa1100/timer.c
+++ b/arch/arm/cpu/sa1100/timer.c
@@ -13,11 +13,6 @@
 #include <common.h>
 #include <SA-1100.h>
 
-int timer_init (void)
-{
-	return 0;
-}
-
 ulong get_timer (ulong base)
 {
 	return get_timer_masked ();
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index c1777dfdc9..fbe599d1ab 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -43,7 +43,7 @@
 #define MT47H128M16RT25E_IOCTRL_VALUE		0x18B
 
 /* Micron MT41J128M16JT-125 */
-#define MT41J128MJT125_EMIF_READ_LATENCY	0x06
+#define MT41J128MJT125_EMIF_READ_LATENCY	0x100006
 #define MT41J128MJT125_EMIF_TIM1		0x0888A39B
 #define MT41J128MJT125_EMIF_TIM2		0x26337FDA
 #define MT41J128MJT125_EMIF_TIM3		0x501F830F
@@ -65,7 +65,7 @@
 #define MT41J256MJT125_EMIF_SDCFG		0x61C04B32
 
 /* Micron MT41J256M8HX-15E */
-#define MT41J256M8HX15E_EMIF_READ_LATENCY	0x06
+#define MT41J256M8HX15E_EMIF_READ_LATENCY	0x100006
 #define MT41J256M8HX15E_EMIF_TIM1		0x0888A39B
 #define MT41J256M8HX15E_EMIF_TIM2		0x26337FDA
 #define MT41J256M8HX15E_EMIF_TIM3		0x501F830F
@@ -97,7 +97,7 @@
 #define MT41K256M16HA125E_IOCTRL_VALUE		0x18B
 
 /* Micron MT41J512M8RH-125 on EVM v1.5 */
-#define MT41J512M8RH125_EMIF_READ_LATENCY	0x06
+#define MT41J512M8RH125_EMIF_READ_LATENCY	0x100006
 #define MT41J512M8RH125_EMIF_TIM1		0x0888A39B
 #define MT41J512M8RH125_EMIF_TIM2		0x26517FDA
 #define MT41J512M8RH125_EMIF_TIM3		0x501F84EF
@@ -113,7 +113,7 @@
 #define MT41J512M8RH125_IOCTRL_VALUE		0x18B
 
 /* Samsung K4B2G1646E-BIH9 */
-#define K4B2G1646EBIH9_EMIF_READ_LATENCY	0x07
+#define K4B2G1646EBIH9_EMIF_READ_LATENCY	0x100007
 #define K4B2G1646EBIH9_EMIF_TIM1		0x0AAAE51B
 #define K4B2G1646EBIH9_EMIF_TIM2		0x2A1D7FDA
 #define K4B2G1646EBIH9_EMIF_TIM3		0x501F83FF
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index 5cd1e95257..2df4114580 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -19,6 +19,7 @@
 #define BOOT_DEVICE_MMC1	7
 #define BOOT_DEVICE_MMC2	8
 #define BOOT_DEVICE_SPI		10
+#define BOOT_DEVICE_USB     13
 #define BOOT_DEVICE_UART	65
 #define BOOT_DEVICE_CPGMAC	71
 #else
@@ -38,9 +39,16 @@
 #endif
 #define BOOT_DEVICE_MMC2_2      0xFF
 
-#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
-#define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1
-#define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC2
+#if defined(CONFIG_AM33XX)
+#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
+#define MMC_BOOT_DEVICES_END   BOOT_DEVICE_MMC2
+#elif defined(CONFIG_AM43XX)
+#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
+#ifdef CONFIG_SPL_USB_SUPPORT
+#define MMC_BOOT_DEVICES_END   BOOT_DEVICE_USB
+#else
+#define MMC_BOOT_DEVICES_END   BOOT_DEVICE_MMC2
+#endif
 #elif defined(CONFIG_TI81XX)
 #define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC2
 #define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC1
diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h
index 6b806ec57f..38cb42a3b3 100644
--- a/arch/arm/include/asm/arch-bcm2835/mbox.h
+++ b/arch/arm/include/asm/arch-bcm2835/mbox.h
@@ -133,6 +133,54 @@ struct bcm2835_mbox_tag_get_arm_mem {
 	} body;
 };
 
+#define BCM2835_MBOX_POWER_DEVID_SDHCI		0
+#define BCM2835_MBOX_POWER_DEVID_UART0		1
+#define BCM2835_MBOX_POWER_DEVID_UART1		2
+#define BCM2835_MBOX_POWER_DEVID_USB_HCD	3
+#define BCM2835_MBOX_POWER_DEVID_I2C0		4
+#define BCM2835_MBOX_POWER_DEVID_I2C1		5
+#define BCM2835_MBOX_POWER_DEVID_I2C2		6
+#define BCM2835_MBOX_POWER_DEVID_SPI		7
+#define BCM2835_MBOX_POWER_DEVID_CCP2TX		8
+
+#define BCM2835_MBOX_POWER_STATE_RESP_ON	(1 << 1)
+/* Device doesn't exist */
+#define BCM2835_MBOX_POWER_STATE_RESP_NODEV	(1 << 1)
+
+#define BCM2835_MBOX_TAG_GET_POWER_STATE	0x00020001
+
+struct bcm2835_mbox_tag_get_power_state {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		struct {
+			u32 device_id;
+		} req;
+		struct {
+			u32 device_id;
+			u32 state;
+		} resp;
+	} body;
+};
+
+#define BCM2835_MBOX_TAG_SET_POWER_STATE	0x00028001
+
+#define BCM2835_MBOX_SET_POWER_STATE_REQ_ON	(1 << 0)
+#define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT	(1 << 1)
+
+struct bcm2835_mbox_tag_set_power_state {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		struct {
+			u32 device_id;
+			u32 state;
+		} req;
+		struct {
+			u32 device_id;
+			u32 state;
+		} resp;
+	} body;
+};
+
 #define BCM2835_MBOX_TAG_GET_CLOCK_RATE	0x00030002
 
 #define BCM2835_MBOX_CLOCK_ID_EMMC	1
diff --git a/arch/arm/include/asm/arch-exynos/ehci.h b/arch/arm/include/asm/arch-exynos/ehci.h
index d79f25c0c3..d2d70bd82b 100644
--- a/arch/arm/include/asm/arch-exynos/ehci.h
+++ b/arch/arm/include/asm/arch-exynos/ehci.h
@@ -29,6 +29,20 @@
 #define EHCICTRL_ENAINCR8			(1 << 27)
 #define EHCICTRL_ENAINCR16			(1 << 26)
 
+#define HSIC_CTRL_REFCLKSEL                     (0x2)
+#define HSIC_CTRL_REFCLKSEL_MASK                (0x3)
+#define HSIC_CTRL_REFCLKSEL_SHIFT               (23)
+
+#define HSIC_CTRL_REFCLKDIV_12                  (0x24)
+#define HSIC_CTRL_REFCLKDIV_MASK                (0x7f)
+#define HSIC_CTRL_REFCLKDIV_SHIFT               (16)
+
+#define HSIC_CTRL_SIDDQ                         (0x1 << 6)
+#define HSIC_CTRL_FORCESLEEP                    (0x1 << 5)
+#define HSIC_CTRL_FORCESUSPEND                  (0x1 << 4)
+#define HSIC_CTRL_UTMISWRST                     (0x1 << 2)
+#define HSIC_CTRL_PHYSWRST                      (0x1 << 0)
+
 /* Register map for PHY control */
 struct exynos_usb_phy {
 	unsigned int usbphyctrl0;
diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h
index 65a5995020..194b93bf56 100644
--- a/arch/arm/include/asm/arch-omap3/omap3.h
+++ b/arch/arm/include/asm/arch-omap3/omap3.h
@@ -140,13 +140,13 @@ struct gpio {
 					 SRAM_OFFSET2)
 #define SRAM_CLK_CODE			(SRAM_VECT_CODE + 64)
 
-#define OMAP3_PUBLIC_SRAM_BASE		0x40208000 /* Works for GP & EMU */
-#define OMAP3_PUBLIC_SRAM_END		0x40210000
+#define NON_SECURE_SRAM_START		0x40208000 /* Works for GP & EMU */
+#define NON_SECURE_SRAM_END		0x40210000
 
 #define LOW_LEVEL_SRAM_STACK		0x4020FFFC
 
 /* scratch area - accessible on both EMU and GP */
-#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA	OMAP3_PUBLIC_SRAM_BASE
+#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA	NON_SECURE_SRAM_START
 
 #define DEBUG_LED1			149	/* gpio */
 #define DEBUG_LED2			150	/* gpio */
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index ce8217f697..fc9472544d 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -30,7 +30,6 @@ void watchdog_init(void);
 u32 get_device_type(void);
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
 void set_muxconf_regs_essential(void);
-void set_muxconf_regs_non_essential(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 590235be09..19fdecec01 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -44,6 +44,7 @@
 #define OMAP5432_CONTROL_ID_CODE_ES1_0		0x0B99802F
 #define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
 #define DRA752_CONTROL_ID_CODE_ES1_0		0x0B99002F
+#define DRA752_CONTROL_ID_CODE_ES1_1		0x1B99002F
 
 /* UART */
 #define UART1_BASE		(OMAP54XX_L4_PER_BASE + 0x6a000)
@@ -204,6 +205,8 @@ struct s32ktimer {
 /* ABB efuse masks */
 #define OMAP5_ABB_FUSE_VSET_MASK		(0x1F << 24)
 #define OMAP5_ABB_FUSE_ENABLE_MASK		(0x1 << 29)
+#define DRA7_ABB_FUSE_VSET_MASK			(0x1F << 20)
+#define DRA7_ABB_FUSE_ENABLE_MASK		(0x1 << 25)
 #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK	(0x1 << 10)
 #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK	(0x1f << 0)
 
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 9e70d48f43..43011a4acd 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -31,7 +31,6 @@ void watchdog_init(void);
 u32 get_device_type(void);
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
 void set_muxconf_regs_essential(void);
-void set_muxconf_regs_non_essential(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index a78f99079b..04925bca1c 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -567,7 +567,6 @@ u32 omap_ddr_clk(void);
 u32 get_sys_clk_index(void);
 void enable_basic_clocks(void);
 void enable_basic_uboot_clocks(void);
-void enable_non_essential_clocks(void);
 void scale_vcores(struct vcores_data const *);
 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
@@ -643,6 +642,7 @@ static inline u8 is_dra7xx(void)
 
 /* DRA7XX */
 #define DRA752_ES1_0	0x07520100
+#define DRA752_ES1_1	0x07520110
 
 /*
  * SRAM scratch space entries
diff --git a/arch/avr32/config.mk b/arch/avr32/config.mk
index 4ab4745edf..b9b96313c5 100644
--- a/arch/avr32/config.mk
+++ b/arch/avr32/config.mk
@@ -6,7 +6,7 @@
 #
 
 CROSS_COMPILE ?= avr32-linux-
-
+PLATFORM_CPPFLAGS += -DCONFIG_AVR32
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000
 
 PLATFORM_RELFLAGS	+= -ffixed-r5 -fPIC -mno-init-got -mrelax
diff --git a/arch/avr32/cpu/pio2.h b/arch/avr32/cpu/pio2.h
deleted file mode 100644
index 9719ea8c43..0000000000
--- a/arch/avr32/cpu/pio2.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Register definitions for Parallel Input/Output Controller
- */
-#ifndef __CPU_AT32AP_PIO2_H__
-#define __CPU_AT32AP_PIO2_H__
-
-/* PIO2 register offsets */
-#define PIO2_PER				0x0000
-#define PIO2_PDR				0x0004
-#define PIO2_PSR				0x0008
-#define PIO2_OER				0x0010
-#define PIO2_ODR				0x0014
-#define PIO2_OSR				0x0018
-#define PIO2_IFER				0x0020
-#define PIO2_IFDR				0x0024
-#define PIO2_ISFR				0x0028
-#define PIO2_SODR				0x0030
-#define PIO2_CODR				0x0034
-#define PIO2_ODSR				0x0038
-#define PIO2_PDSR				0x003c
-#define PIO2_IER				0x0040
-#define PIO2_IDR				0x0044
-#define PIO2_IMR				0x0048
-#define PIO2_ISR				0x004c
-#define PIO2_MDER				0x0050
-#define PIO2_MDDR				0x0054
-#define PIO2_MDSR				0x0058
-#define PIO2_PUDR				0x0060
-#define PIO2_PUER				0x0064
-#define PIO2_PUSR				0x0068
-#define PIO2_ASR				0x0070
-#define PIO2_BSR				0x0074
-#define PIO2_ABSR				0x0078
-#define PIO2_OWER				0x00a0
-#define PIO2_OWDR				0x00a4
-#define PIO2_OWSR				0x00a8
-
-/* Register access macros */
-#define pio2_readl(base,reg)				\
-	readl((void *)base + PIO2_##reg)
-#define pio2_writel(base,reg,value)			\
-	writel((value), (void *)base + PIO2_##reg)
-
-#endif /* __CPU_AT32AP_PIO2_H__ */
diff --git a/arch/avr32/include/asm/arch-at32ap700x/gpio-impl.h b/arch/avr32/include/asm/arch-at32ap700x/gpio-impl.h
deleted file mode 100644
index 8801bd006c..0000000000
--- a/arch/avr32/include/asm/arch-at32ap700x/gpio-impl.h
+++ /dev/null
@@ -1,86 +0,0 @@
-#ifndef __ASM_AVR32_ARCH_GPIO_IMPL_H__
-#define __ASM_AVR32_ARCH_GPIO_IMPL_H__
-
-/* Register offsets */
-struct gpio_regs {
-	u32	GPER;
-	u32	GPERS;
-	u32	GPERC;
-	u32	GPERT;
-	u32	PMR0;
-	u32	PMR0S;
-	u32	PMR0C;
-	u32	PMR0T;
-	u32	PMR1;
-	u32	PMR1S;
-	u32	PMR1C;
-	u32	PMR1T;
-	u32	__reserved0[4];
-	u32	ODER;
-	u32	ODERS;
-	u32	ODERC;
-	u32	ODERT;
-	u32	OVR;
-	u32	OVRS;
-	u32	OVRC;
-	u32	OVRT;
-	u32	PVR;
-	u32	__reserved_PVRS;
-	u32	__reserved_PVRC;
-	u32	__reserved_PVRT;
-	u32	PUER;
-	u32	PUERS;
-	u32	PUERC;
-	u32	PUERT;
-	u32	PDER;
-	u32	PDERS;
-	u32	PDERC;
-	u32	PDERT;
-	u32	IER;
-	u32	IERS;
-	u32	IERC;
-	u32	IERT;
-	u32	IMR0;
-	u32	IMR0S;
-	u32	IMR0C;
-	u32	IMR0T;
-	u32	IMR1;
-	u32	IMR1S;
-	u32	IMR1C;
-	u32	IMR1T;
-	u32	GFER;
-	u32	GFERS;
-	u32	GFERC;
-	u32	GFERT;
-	u32	IFR;
-	u32	__reserved_IFRS;
-	u32	IFRC;
-	u32	__reserved_IFRT;
-	u32	ODMER;
-	u32	ODMERS;
-	u32	ODMERC;
-	u32	ODMERT;
-	u32	__reserved1[4];
-	u32	ODCR0;
-	u32	ODCR0S;
-	u32	ODCR0C;
-	u32	ODCR0T;
-	u32	ODCR1;
-	u32	ODCR1S;
-	u32	ODCR1C;
-	u32	ODCR1T;
-	u32	__reserved2[4];
-	u32	OSRR0;
-	u32	OSRR0S;
-	u32	OSRR0C;
-	u32	OSRR0T;
-	u32	__reserved3[8];
-	u32	STER;
-	u32	STERS;
-	u32	STERC;
-	u32	STERT;
-	u32	__reserved4[35];
-	u32	VERSION;
-};
-
-#endif /* __ASM_AVR32_ARCH_GPIO_IMPL_H__ */
diff --git a/arch/avr32/include/asm/arch-common/portmux-gpio.h b/arch/avr32/include/asm/arch-common/portmux-gpio.h
deleted file mode 100644
index fb01a17fc1..0000000000
--- a/arch/avr32/include/asm/arch-common/portmux-gpio.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (C) 2008 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __AVR32_PORTMUX_GPIO_H__
-#define __AVR32_PORTMUX_GPIO_H__
-
-#include <asm/io.h>
-
-/* Register layout for this specific device */
-#include <asm/arch/gpio-impl.h>
-
-/* Register access macros */
-#define gpio_readl(port, reg)						\
-	__raw_readl(&((struct gpio_regs *)port)->reg)
-#define gpio_writel(gpio, reg, value)					\
-	__raw_writel(value, &((struct gpio_regs *)port)->reg)
-
-/* Portmux API starts here. See doc/README.AVR32-port-muxing */
-
-enum portmux_function {
-	PORTMUX_FUNC_A,
-	PORTMUX_FUNC_B,
-	PORTMUX_FUNC_C,
-	PORTMUX_FUNC_D,
-};
-
-#define PORTMUX_DIR_INPUT	(0 << 0)
-#define PORTMUX_DIR_OUTPUT	(1 << 0)
-#define PORTMUX_INIT_LOW	(0 << 1)
-#define PORTMUX_INIT_HIGH	(1 << 1)
-#define PORTMUX_PULL_UP		(1 << 2)
-#define PORTMUX_PULL_DOWN	(2 << 2)
-#define PORTMUX_BUSKEEPER	(3 << 2)
-#define PORTMUX_DRIVE_MIN	(0 << 4)
-#define PORTMUX_DRIVE_LOW	(1 << 4)
-#define PORTMUX_DRIVE_HIGH	(2 << 4)
-#define PORTMUX_DRIVE_MAX	(3 << 4)
-#define PORTMUX_OPEN_DRAIN	(1 << 6)
-
-void portmux_select_peripheral(void *port, unsigned long pin_mask,
-		enum portmux_function func, unsigned long flags);
-void portmux_select_gpio(void *port, unsigned long pin_mask,
-		unsigned long flags);
-
-/* Internal helper functions */
-
-static inline void *gpio_pin_to_port(unsigned int pin)
-{
-	return (void *)GPIO_BASE + (pin >> 5) * 0x200;
-}
-
-static inline void __gpio_set_output_value(void *port, unsigned int pin,
-		int value)
-{
-	if (value)
-		gpio_writel(port, OVRS, 1 << pin);
-	else
-		gpio_writel(port, OVRC, 1 << pin);
-}
-
-static inline int __gpio_get_input_value(void *port, unsigned int pin)
-{
-	return (gpio_readl(port, PVR) >> pin) & 1;
-}
-
-void gpio_set_output_value(unsigned int pin, int value);
-int gpio_get_input_value(unsigned int pin);
-
-/* GPIO API starts here */
-
-/*
- * GCC doesn't realize that the constant case is extremely trivial,
- * so we need to help it make the right decision by using
- * always_inline.
- */
-__attribute__((always_inline))
-static inline void gpio_set_value(unsigned int pin, int value)
-{
-	if (__builtin_constant_p(pin))
-		__gpio_set_output_value(gpio_pin_to_port(pin),
-				pin & 0x1f, value);
-	else
-		gpio_set_output_value(pin, value);
-}
-
-__attribute__((always_inline))
-static inline int gpio_get_value(unsigned int pin)
-{
-	if (__builtin_constant_p(pin))
-		return __gpio_get_input_value(gpio_pin_to_port(pin),
-				pin & 0x1f);
-	else
-		return gpio_get_input_value(pin);
-}
-
-#endif /* __AVR32_PORTMUX_GPIO_H__ */
diff --git a/arch/blackfin/include/asm/mach-common/bits/lockbox.h b/arch/blackfin/include/asm/mach-common/bits/lockbox.h
deleted file mode 100644
index 17d22ab57f..0000000000
--- a/arch/blackfin/include/asm/mach-common/bits/lockbox.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Lockbox/Security Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_LOCKBOX__
-#define __BFIN_PERIPHERAL_LOCKBOX__
-
-#ifndef __ASSEMBLY__
-
-#include "bootrom.h"
-
-/* SESR argument structure. Expected to reside at 0xFF900018. */
-typedef struct SESR_args {
-	unsigned short  usFlags;            /* security firmware flags            */
-	unsigned short  usIRQMask;          /* interrupt mask                     */
-	unsigned long   ulMessageSize;      /* message length in bytes            */
-	unsigned long   ulSFEntryPoint;     /* entry point of secure function     */
-	unsigned long   ulMessagePtr;       /* pointer to the buffer containing
-					       the digital signature and message  */
-	unsigned long   ulReserved1;        /* reserved                           */
-	unsigned long   ulReserved2;        /* reserved                           */
-} tSESR_args;
-
-/* Secure Entry Service Routine */
-static void (* const sesr)(void) = (void *)_BOOTROM_SESR;
-
-#endif
-
-/* SESR flags argument bitfields */
-#define SESR_FLAGS_STAY_AT_NMI              0x0000
-#define SESR_FLAGS_DROP_BELOW_NMI           0x0001
-#define SESR_FLAGS_NO_SF_DMA                0x0000
-#define SESR_FLAGS_DMA_SF_TO_RUN_DEST       0x0002
-#define SESR_FLAGS_USE_ADI_PUB_KEY          0x0000
-#define SESR_FLAGS_USE_CUST_PUB_KEY         0x0100
-
-/* Bit masks for SECURE_SYSSWT */
-#define EMUDABL                0x00000001    /* Emulation Disable */
-#define RSTDABL                0x00000002    /* Reset Disable */
-#define L1IDABL                0x0000001c    /* L1 Instruction Memory Disable */
-#define L1DADABL               0x000000e0    /* L1 Data Bank A Memory Disable */
-#define L1DBDABL               0x00000700    /* L1 Data Bank B Memory Disable */
-#define DMA0OVR                0x00000800    /* DMA0 Memory Access Override */
-#define DMA1OVR                0x00001000    /* DMA1 Memory Access Override */
-#define EMUOVR                 0x00004000    /* Emulation Override */
-#define OTPSEN                 0x00008000    /* OTP Secrets Enable */
-#define L2DABL                 0x00070000    /* L2 Memory Disable */
-
-/* Bit masks for SECURE_CONTROL */
-#define SECURE0                0x0001        /* SECURE 0 */
-#define SECURE1                0x0002        /* SECURE 1 */
-#define SECURE2                0x0004        /* SECURE 2 */
-#define SECURE3                0x0008        /* SECURE 3 */
-
-/* Bit masks for SECURE_STATUS */
-#define SECMODE                0x0003        /* Secured Mode Control State */
-#define NMI                    0x0004        /* Non Maskable Interrupt */
-#define AFVALID                0x0008        /* Authentication Firmware Valid */
-#define AFEXIT                 0x0010        /* Authentication Firmware Exit */
-#define SECSTAT                0x00e0        /* Secure Status */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/sport.h b/arch/blackfin/include/asm/mach-common/bits/sport.h
deleted file mode 100644
index 88e7a5d324..0000000000
--- a/arch/blackfin/include/asm/mach-common/bits/sport.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * SPORT Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_SPORT__
-#define __BFIN_PERIPHERAL_SPORT__
-
-/* SPORTx_TCR1 Masks */
-#define TSPEN			0x0001	/* TX enable */
-#define ITCLK			0x0002	/* Internal TX Clock Select */
-#define TDTYPE			0x000C	/* TX Data Formatting Select */
-#define DTYPE_NORM		0x0004	/* Data Format Normal */
-#define DTYPE_ULAW		0x0008	/* Compand Using u-Law */
-#define DTYPE_ALAW		0x000C	/* Compand Using A-Law */
-#define TLSBIT			0x0010	/* TX Bit Order */
-#define ITFS			0x0200	/* Internal TX Frame Sync Select */
-#define TFSR			0x0400	/* TX Frame Sync Required Select */
-#define DITFS			0x0800	/* Data Independent TX Frame Sync Select */
-#define LTFS			0x1000	/* Low TX Frame Sync Select */
-#define LATFS			0x2000	/* Late TX Frame Sync Select */
-#define TCKFE			0x4000	/* TX Clock Falling Edge Select */
-
-/* SPORTx_TCR2 Masks */
-#define SLEN			0x001F	/* TX Word Length */
-#define TXSE			0x0100	/* TX Secondary Enable */
-#define TSFSE			0x0200	/* TX Stereo Frame Sync Enable */
-#define TRFST			0x0400	/* TX Right-First Data Order */
-
-/* SPORTx_RCR1 Masks */
-#define RSPEN			0x0001	/* RX enable */
-#define IRCLK			0x0002	/* Internal RX Clock Select */
-#define RDTYPE			0x000C	/* RX Data Formatting Select */
-#define DTYPE_NORM		0x0004	/* Data Format Normal */
-#define DTYPE_ULAW		0x0008	/* Compand Using u-Law */
-#define DTYPE_ALAW		0x000C	/* Compand Using A-Law */
-#define RLSBIT			0x0010	/* RX Bit Order */
-#define IRFS			0x0200	/* Internal RX Frame Sync Select */
-#define RFSR			0x0400	/* RX Frame Sync Required Select */
-#define LRFS			0x1000	/* Low RX Frame Sync Select */
-#define LARFS			0x2000	/* Late RX Frame Sync Select */
-#define RCKFE			0x4000	/* RX Clock Falling Edge Select */
-
-/* SPORTx_RCR2 Masks */
-#define SLEN			0x001F	/* RX Word Length */
-#define RXSE			0x0100	/* RX Secondary Enable */
-#define RSFSE			0x0200	/* RX Stereo Frame Sync Enable */
-#define RRFST			0x0400	/* Right-First Data Order */
-
-/* SPORTx_STAT Masks */
-#define RXNE			0x0001	/* RX FIFO Not Empty Status */
-#define RUVF			0x0002	/* RX Underflow Status */
-#define ROVF			0x0004	/* RX Overflow Status */
-#define TXF			0x0008	/* TX FIFO Full Status */
-#define TUVF			0x0010	/* TX Underflow Status */
-#define TOVF			0x0020	/* TX Overflow Status */
-#define TXHRE			0x0040	/* TX Hold Register Empty */
-
-/* SPORTx_MCMC1 Masks */
-#define WSIZE			0xF000	/* Multichannel Window Size Field */
-#define WOFF			0x03FF	/* Multichannel Window Offset Field */
-
-/* SPORTx_MCMC2 Masks */
-#define MCCRM			0x0003	/* Multichannel Clock Recovery Mode */
-#define REC_BYPASS		0x0000	/* Bypass Mode (No Clock Recovery) */
-#define REC_2FROM4		0x0002	/* Recover 2 MHz Clock from 4 MHz Clock */
-#define REC_8FROM16		0x0003	/* Recover 8 MHz Clock from 16 MHz Clock */
-#define MCDTXPE			0x0004	/* Multichannel DMA Transmit Packing */
-#define MCDRXPE			0x0008	/* Multichannel DMA Receive Packing */
-#define MCMEN			0x0010	/* Multichannel Frame Mode Enable */
-#define FSDR			0x0080	/* Multichannel Frame Sync to Data Relationship */
-#define MFD			0xF000	/* Multichannel Frame Delay */
-#define MFD_0			0x0000	/* Multichannel Frame Delay = 0 */
-#define MFD_1			0x1000	/* Multichannel Frame Delay = 1 */
-#define MFD_2			0x2000	/* Multichannel Frame Delay = 2 */
-#define MFD_3			0x3000	/* Multichannel Frame Delay = 3 */
-#define MFD_4			0x4000	/* Multichannel Frame Delay = 4 */
-#define MFD_5			0x5000	/* Multichannel Frame Delay = 5 */
-#define MFD_6			0x6000	/* Multichannel Frame Delay = 6 */
-#define MFD_7			0x7000	/* Multichannel Frame Delay = 7 */
-#define MFD_8			0x8000	/* Multichannel Frame Delay = 8 */
-#define MFD_9			0x9000	/* Multichannel Frame Delay = 9 */
-#define MFD_10			0xA000	/* Multichannel Frame Delay = 10 */
-#define MFD_11			0xB000	/* Multichannel Frame Delay = 11 */
-#define MFD_12			0xC000	/* Multichannel Frame Delay = 12 */
-#define MFD_13			0xD000	/* Multichannel Frame Delay = 13 */
-#define MFD_14			0xE000	/* Multichannel Frame Delay = 14 */
-#define MFD_15			0xF000	/* Multichannel Frame Delay = 15 */
-
-#endif
diff --git a/arch/powerpc/cpu/mpc5xx/start.S b/arch/powerpc/cpu/mpc5xx/start.S
index 92f956db8d..6b196de355 100644
--- a/arch/powerpc/cpu/mpc5xx/start.S
+++ b/arch/powerpc/cpu/mpc5xx/start.S
@@ -19,9 +19,6 @@
 #include <mpc5xx.h>
 #include <version.h>
 
-#define CONFIG_5xx 1		/* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S
index 517b5808fe..02c706ec63 100644
--- a/arch/powerpc/cpu/mpc5xxx/start.S
+++ b/arch/powerpc/cpu/mpc5xxx/start.S
@@ -14,9 +14,6 @@
 #include <mpc5xxx.h>
 #include <version.h>
 
-#define CONFIG_MPC5xxx 1	/* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/arch/powerpc/cpu/mpc824x/drivers/i2c_export.h b/arch/powerpc/cpu/mpc824x/drivers/i2c_export.h
deleted file mode 100644
index 6264d189bb..0000000000
--- a/arch/powerpc/cpu/mpc824x/drivers/i2c_export.h
+++ /dev/null
@@ -1,103 +0,0 @@
-#ifndef I2C_EXPORT_H
-#define I2C_EXPORT_H
-
-/****************************************************
- *
- * Copyright Motrola 1999
- *
- ****************************************************/
-
-/* These are the defined return values for the I2C_do_transaction function.
- * Any non-zero value indicates failure.  Failure modes can be added for
- * more detailed error reporting.
- */
-typedef enum _i2c_status
-{
- I2C_SUCCESS     = 0,
- I2C_ERROR,
-} I2C_Status;
-
-/* These are the defined tasks for I2C_do_transaction.
- * Modes for SLAVE_RCV and SLAVE_XMIT will be added.
- */
-typedef enum _i2c_transaction_mode
-{
-	I2C_MASTER_RCV =  0,
-	I2C_MASTER_XMIT = 1,
-} I2C_TRANSACTION_MODE;
-
-typedef enum _i2c_interrupt_mode
-{
-	I2C_INT_DISABLE =  0,
-	I2C_INT_ENABLE = 1,
-} I2C_INTERRUPT_MODE;
-
-typedef enum _i2c_stop
-{
-	I2C_NO_STOP =  0,
-	I2C_STOP = 1,
-} I2C_STOP_MODE;
-
-typedef enum _i2c_restart
-{
-	I2C_NO_RESTART =  0,
-	I2C_RESTART = 1,
-} I2C_RESTART_MODE;
-
-/******************** App. API ********************
- * The application API is for user level application
- * to use the functionality provided by I2C driver.
- * This is a "generic" I2C interface, it should contain
- * nothing specific to the Kahlua implementation.
- * Only the generic functions are exported by the library.
- *
- * Note: Its App.s responsibility to swap the data
- *       byte. In our API, we just transfer whatever
- *       we are given
- **************************************************/
-
-
-/*  Initialize I2C unit with the following:
- *  driver's slave address
- *  interrupt enabled
- *  optional pointer to application layer print function
- *
- *  These parameters may be added:
- *  desired clock rate
- *  digital filter frequency sampling rate
- *
- *  This function must be called before I2C unit can be used.
- */
-extern I2C_Status I2C_Initialize(
-	unsigned char addr,            /* driver's I2C slave address */
-	I2C_INTERRUPT_MODE en_int,     /* 1 - enable I2C interrupt
-					* 0 - disable I2C interrupt
-					*/
-	int (*app_print_function)(char *,...)); /* pointer to optional "printf"
-						 * provided by application
-						 */
-
-/* Perform the given I2C transaction, only MASTER_XMIT and MASTER_RCV
- * are implemented.  Both are only in polling mode.
- *
- * en_int controls interrupt/polling mode
- * act is the type of transaction
- * addr is the I2C address of the slave device
- * len is the length of data to send or receive
- * buffer is the address of the data buffer
- * stop = I2C_NO_STOP, don't signal STOP at end of transaction
- *        I2C_STOP, signal STOP at end of transaction
- * retry is the timeout retry value, currently ignored
- * rsta = I2C_NO_RESTART, this is not continuation of existing transaction
- *        I2C_RESTART, this is a continuation of existing transaction
- */
-extern I2C_Status I2C_do_transaction( I2C_INTERRUPT_MODE en_int,
-				      I2C_TRANSACTION_MODE act,
-				      unsigned char i2c_addr,
-				      unsigned char data_addr,
-				      int len,
-				      char *buffer,
-				      I2C_STOP_MODE stop,
-				      int retry,
-				      I2C_RESTART_MODE rsta);
-#endif
diff --git a/arch/powerpc/cpu/mpc824x/start.S b/arch/powerpc/cpu/mpc824x/start.S
index 6f397a44c6..b1fb062a08 100644
--- a/arch/powerpc/cpu/mpc824x/start.S
+++ b/arch/powerpc/cpu/mpc824x/start.S
@@ -26,8 +26,6 @@
 #include <mpc824x.h>
 #include <version.h>
 
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/arch/powerpc/cpu/mpc8260/kgdb.S b/arch/powerpc/cpu/mpc8260/kgdb.S
index 5a298f9d05..dd04d6bd6f 100644
--- a/arch/powerpc/cpu/mpc8260/kgdb.S
+++ b/arch/powerpc/cpu/mpc8260/kgdb.S
@@ -10,7 +10,6 @@
 #include <version.h>
 
 #define CONFIG_8260 1		/* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
 
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
diff --git a/arch/powerpc/cpu/mpc8260/speed.h b/arch/powerpc/cpu/mpc8260/speed.h
deleted file mode 100644
index f1b10bf25e..0000000000
--- a/arch/powerpc/cpu/mpc8260/speed.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*-----------------------------------------------------------------------
- * Timer value for timer 2, ICLK = 10
- *
- * SPEED_FCOUNT2 =  GCLK / (16 * (TIMER_TMR_PS + 1))
- * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
- *
- * SPEED_FCOUNT2	timer 2 counting frequency
- * GCLK			CPU clock
- * SPEED_TMR2_PS	prescaler
- */
-#define SPEED_TMR2_PS	(250 - 1)	/* divide by 250	*/
-
-/*-----------------------------------------------------------------------
- * Timer value for PIT
- *
- * PIT_TIME = SPEED_PITC / PITRTCLK
- * PITRTCLK = 8192
- */
-#define SPEED_PITC	(82 << 16)	/* start counting from 82	*/
-
-/*
- * The new value for PTA is calculated from
- *
- *	PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
- *
- * gclk		CPU clock (not bus clock !)
- * Trefresh	Refresh cycle * 4 (four word bursts used)
- * DFBRG	For normal mode (no clock reduction) always 0
- * PTP		Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
- * NCS		Number of SDRAM banks (chip selects) on this UPM.
- */
diff --git a/arch/powerpc/cpu/mpc8260/start.S b/arch/powerpc/cpu/mpc8260/start.S
index 1269291c45..65510fa760 100644
--- a/arch/powerpc/cpu/mpc8260/start.S
+++ b/arch/powerpc/cpu/mpc8260/start.S
@@ -15,7 +15,6 @@
 #include <version.h>
 
 #define CONFIG_8260 1		/* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
 
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index b4fafe65ef..36724e5aa5 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -20,7 +20,6 @@
 #include <version.h>
 
 #define CONFIG_83XX	1		/* needed for Linux kernel header files*/
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file */
 
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
@@ -120,6 +119,11 @@ disable_addr_trans:
 	mtspr	SRR1, r3
 	rfi
 
+	.globl get_svr
+get_svr:
+	mfspr	r3, SVR
+	blr
+
 	.globl get_pvr
 get_pvr:
 	mfspr	r3, PVR
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 1e5a43f0e0..7693899058 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -156,7 +156,7 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	puts("Work-around for Erratum CPU-A003999 enabled\n");
 #endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
-	puts("Work-around for Erratum DDR-A003473 enabled\n");
+	puts("Work-around for Erratum DDR-A003474 enabled\n");
 #endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
 	puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
diff --git a/arch/powerpc/cpu/mpc85xx/config.mk b/arch/powerpc/cpu/mpc85xx/config.mk
index 72c964cd15..1470f95ff1 100644
--- a/arch/powerpc/cpu/mpc85xx/config.mk
+++ b/arch/powerpc/cpu/mpc85xx/config.mk
@@ -5,7 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_CPPFLAGS += -Wa,-me500 -msoft-float -mno-string
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -Wa,-me500 -msoft-float -mno-string
 
 # -mspe=yes is needed to have -mno-spe accepted by a buggy GCC;
 # see "[PATCH,rs6000] make -mno-spe work as expected" on
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index c15e83b521..fcfba7ec19 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -10,8 +10,6 @@
 #include <mpc85xx.h>
 #include <version.h>
 
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index db84d10c5b..dbbd8e588c 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -17,8 +17,6 @@
 #include <mpc85xx.h>
 #include <version.h>
 
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index bc132673a5..acaa0939ab 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -57,7 +57,14 @@ SECTIONS
 	. = ALIGN(8);
 	__init_begin = .;
 	__init_end = .;
-/* FIXME for non-NAND SPL */
+
+/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+	.bootpg ADDR(.text) - 0x1000 :
+	{
+		KEEP(*(.bootpg))
+	} :text = 0xffff
+#else
 #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
 	.bootpg ADDR(.text) + 0x1000 :
 	{
@@ -69,12 +76,6 @@ SECTIONS
 #else
 #error unknown NAND controller
 #endif
-#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
-	.bootpg ADDR(.text) - 0x1000 :
-	{
-		KEEP(*(.bootpg))
-	} :text = 0xffff
-#else
 	.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
 		KEEP(*(.resetvec))
 	} = 0xffff
diff --git a/arch/powerpc/cpu/mpc86xx/config.mk b/arch/powerpc/cpu/mpc86xx/config.mk
index 69a0b96ead..4c7235fcde 100644
--- a/arch/powerpc/cpu/mpc86xx/config.mk
+++ b/arch/powerpc/cpu/mpc86xx/config.mk
@@ -5,4 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_CPPFLAGS += -mstring -maltivec -mabi=altivec -msoft-float
+PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -mstring -maltivec -mabi=altivec -msoft-float
diff --git a/arch/powerpc/cpu/mpc8xx/kgdb.S b/arch/powerpc/cpu/mpc8xx/kgdb.S
index ea27d59a6c..e774d1e70a 100644
--- a/arch/powerpc/cpu/mpc8xx/kgdb.S
+++ b/arch/powerpc/cpu/mpc8xx/kgdb.S
@@ -9,9 +9,6 @@
 #include <mpc8xx.h>
 #include <version.h>
 
-#define CONFIG_8xx 1		/* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S
index 9869bbd183..f8aa93d611 100644
--- a/arch/powerpc/cpu/mpc8xx/start.S
+++ b/arch/powerpc/cpu/mpc8xx/start.S
@@ -26,9 +26,6 @@
 #include <mpc8xx.h>
 #include <version.h>
 
-#define CONFIG_8xx 1		/* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/arch/powerpc/cpu/ppc4xx/dcr.S b/arch/powerpc/cpu/ppc4xx/dcr.S
index 0d99391dfb..6b13528c9a 100644
--- a/arch/powerpc/cpu/ppc4xx/dcr.S
+++ b/arch/powerpc/cpu/ppc4xx/dcr.S
@@ -10,8 +10,6 @@
 
 #include <asm/ppc4xx.h>
 
-#define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/arch/powerpc/cpu/ppc4xx/kgdb.S b/arch/powerpc/cpu/ppc4xx/kgdb.S
index dbc4a6c881..f274c5d564 100644
--- a/arch/powerpc/cpu/ppc4xx/kgdb.S
+++ b/arch/powerpc/cpu/ppc4xx/kgdb.S
@@ -10,7 +10,6 @@
 #include <version.h>
 
 #define CONFIG_405GP 1		/* needed for Linux kernel header files */
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
 
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 38bbc5a9bc..e72c37c75b 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -31,8 +31,6 @@
 #include <asm/ppc4xx.h>
 #include <version.h>
 
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 54ce2f053c..be1d9d2a67 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -152,6 +152,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x10
+#define CONFIG_ESDHC_HC_BLK_ADDR
 
 /* P1011 is single core version of P1020 */
 #elif defined(CONFIG_P1011)
@@ -552,6 +553,7 @@
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_ESDHC_HC_BLK_ADDR
 
 #elif defined(CONFIG_BSC9132)
 #define CONFIG_MAX_CPUS			2
@@ -575,6 +577,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x11
+#define CONFIG_ESDHC_HC_BLK_ADDR
 
 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
 #define CONFIG_E6500
diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h
index 3cac2d4310..a59091977e 100644
--- a/arch/powerpc/include/asm/fsl_errata.h
+++ b/arch/powerpc/include/asm/fsl_errata.h
@@ -15,7 +15,11 @@ static inline bool has_erratum_a006379(void)
 {
 	u32 svr = get_svr();
 	if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) ||
-	    ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2))
+	    ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) ||
+	    ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) ||
+	    ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) ||
+	    ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) ||
+	    ((SVR_SOC_VER(svr) == SVR_T2081) && SVR_MAJ(svr) <= 1))
 		return true;
 
 	return false;
diff --git a/arch/powerpc/include/asm/iopin_85xx.h b/arch/powerpc/include/asm/iopin_85xx.h
deleted file mode 100644
index 0f07ba355e..0000000000
--- a/arch/powerpc/include/asm/iopin_85xx.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * MPC85xx I/O port pin manipulation functions
- */
-
-#ifndef _ASM_IOPIN_85xx_H_
-#define _ASM_IOPIN_85xx_H_
-
-#include <linux/types.h>
-#include <asm/immap_85xx.h>
-
-#ifdef __KERNEL__
-
-typedef struct {
-	u_char port:2;		/* port number (A=0, B=1, C=2, D=3) */
-	u_char pin:5;		/* port pin (0-31) */
-	u_char flag:1;		/* for whatever */
-} iopin_t;
-
-#define IOPIN_PORTA	0
-#define IOPIN_PORTB	1
-#define IOPIN_PORTC	2
-#define IOPIN_PORTD	3
-
-extern __inline__ void iopin_set_high (iopin_t * iopin)
-{
-	volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
-	datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-extern __inline__ void iopin_set_low (iopin_t * iopin)
-{
-	volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
-	datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-extern __inline__ uint iopin_is_high (iopin_t * iopin)
-{
-	volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
-	return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-extern __inline__ uint iopin_is_low (iopin_t * iopin)
-{
-	volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
-	return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-extern __inline__ void iopin_set_out (iopin_t * iopin)
-{
-	volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
-	dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-extern __inline__ void iopin_set_in (iopin_t * iopin)
-{
-	volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
-	dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-extern __inline__ uint iopin_is_out (iopin_t * iopin)
-{
-	volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
-	return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-extern __inline__ uint iopin_is_in (iopin_t * iopin)
-{
-	volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
-	return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-extern __inline__ void iopin_set_odr (iopin_t * iopin)
-{
-	volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
-	odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-extern __inline__ void iopin_set_act (iopin_t * iopin)
-{
-	volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
-	odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-extern __inline__ uint iopin_is_odr (iopin_t * iopin)
-{
-	volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
-	return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-extern __inline__ uint iopin_is_act (iopin_t * iopin)
-{
-	volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
-	return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-extern __inline__ void iopin_set_ded (iopin_t * iopin)
-{
-	volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
-	parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-extern __inline__ void iopin_set_gen (iopin_t * iopin)
-{
-	volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
-	parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-extern __inline__ uint iopin_is_ded (iopin_t * iopin)
-{
-	volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
-	return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-extern __inline__ uint iopin_is_gen (iopin_t * iopin)
-{
-	volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
-	return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-extern __inline__ void iopin_set_opt2 (iopin_t * iopin)
-{
-	volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
-	sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
-}
-
-extern __inline__ void iopin_set_opt1 (iopin_t * iopin)
-{
-	volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
-	sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
-}
-
-extern __inline__ uint iopin_is_opt2 (iopin_t * iopin)
-{
-	volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
-	return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
-}
-
-extern __inline__ uint iopin_is_opt1 (iopin_t * iopin)
-{
-	volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
-	return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
-}
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_IOPIN_85xx_H_ */
diff --git a/arch/powerpc/include/asm/pnp.h b/arch/powerpc/include/asm/pnp.h
deleted file mode 100644
index 22ceba2253..0000000000
--- a/arch/powerpc/include/asm/pnp.h
+++ /dev/null
@@ -1,643 +0,0 @@
-/* 11/02/95                                                                   */
-/*----------------------------------------------------------------------------*/
-/*      Plug and Play header definitions                                      */
-/*----------------------------------------------------------------------------*/
-
-/* Structure map for PnP on PowerPC Reference Platform                        */
-/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993.  It        */
-/* (or later versions) is available on Compuserve in the PLUGPLAY area.       */
-/* This code has extensions to that specification, namely new short and       */
-/* long tag types for platform dependent information                          */
-
-/* Warning: LE notation used throughout this file                             */
-
-/* For enum's: if given in hex then they are bit significant, i.e.            */
-/* only one bit is on for each enum                                           */
-
-#ifndef _PNP_
-#define _PNP_
-
-#ifndef __ASSEMBLY__
-#define MAX_MEM_REGISTERS 9
-#define MAX_IO_PORTS 20
-#define MAX_IRQS 7
-/*#define MAX_DMA_CHANNELS 7*/
-
-/* Interrupt controllers */
-
-#define PNPinterrupt0 "PNP0000"      /* AT Interrupt Controller               */
-#define PNPinterrupt1 "PNP0001"      /* EISA Interrupt Controller             */
-#define PNPinterrupt2 "PNP0002"      /* MCA Interrupt Controller              */
-#define PNPinterrupt3 "PNP0003"      /* APIC                                  */
-#define PNPExtInt     "IBM000D"      /* PowerPC Extended Interrupt Controller */
-
-/* Timers */
-
-#define PNPtimer0     "PNP0100"      /* AT Timer                              */
-#define PNPtimer1     "PNP0101"      /* EISA Timer                            */
-#define PNPtimer2     "PNP0102"      /* MCA Timer                             */
-
-/* DMA controllers */
-
-#define PNPdma0       "PNP0200"      /* AT DMA Controller                     */
-#define PNPdma1       "PNP0201"      /* EISA DMA Controller                   */
-#define PNPdma2       "PNP0202"      /* MCA DMA Controller                    */
-
-/* start of August 15, 1994 additions */
-/* CMOS */
-#define PNPCMOS       "IBM0009"      /* CMOS                                  */
-
-/* L2 Cache */
-#define PNPL2         "IBM0007"      /* L2 Cache                              */
-
-/* NVRAM */
-#define PNPNVRAM      "IBM0008"      /* NVRAM                                 */
-
-/* Power Management */
-#define PNPPM         "IBM0005"      /* Power Management                      */
-/* end of August 15, 1994 additions */
-
-/* Keyboards */
-
-#define PNPkeyboard0  "PNP0300"      /* IBM PC/XT KB Cntlr (83 key, no mouse) */
-#define PNPkeyboard1  "PNP0301"      /* Olivetti ICO (102 key)                */
-#define PNPkeyboard2  "PNP0302"      /* IBM PC/AT KB Cntlr (84 key)           */
-#define PNPkeyboard3  "PNP0303"      /* IBM Enhanced (101/2 key, PS/2 mouse)  */
-#define PNPkeyboard4  "PNP0304"      /* Nokia 1050 KB Cntlr                   */
-#define PNPkeyboard5  "PNP0305"      /* Nokia 9140 KB Cntlr                   */
-#define PNPkeyboard6  "PNP0306"      /* Standard Japanese KB Cntlr            */
-#define PNPkeyboard7  "PNP0307"      /* Microsoft Windows (R) KB Cntlr        */
-
-/* Parallel port controllers */
-
-#define PNPparallel0 "PNP0400"       /* Standard LPT Parallel Port            */
-#define PNPparallel1 "PNP0401"       /* ECP Parallel Port                     */
-#define PNPepp       "IBM001C"       /* EPP Parallel Port                     */
-
-/* Serial port controllers */
-
-#define PNPserial0   "PNP0500"       /* Standard PC Serial port               */
-#define PNPSerial1   "PNP0501"       /* 16550A Compatible Serial port         */
-
-/* Disk controllers */
-
-#define PNPdisk0     "PNP0600"       /* Generic ESDI/IDE/ATA Compat HD Cntlr  */
-#define PNPdisk1     "PNP0601"       /* Plus Hardcard II                      */
-#define PNPdisk2     "PNP0602"       /* Plus Hardcard IIXL/EZ                 */
-
-/* Diskette controllers */
-
-#define PNPdiskette0 "PNP0700"       /* PC Standard Floppy Disk Controller    */
-
-/* Display controllers */
-
-#define PNPdisplay0  "PNP0900"       /* VGA Compatible                        */
-#define PNPdisplay1  "PNP0901"       /* Video Seven VGA                       */
-#define PNPdisplay2  "PNP0902"       /* 8514/A Compatible                     */
-#define PNPdisplay3  "PNP0903"       /* Trident VGA                           */
-#define PNPdisplay4  "PNP0904"       /* Cirrus Logic Laptop VGA               */
-#define PNPdisplay5  "PNP0905"       /* Cirrus Logic VGA                      */
-#define PNPdisplay6  "PNP0906"       /* Tseng ET4000 or ET4000/W32            */
-#define PNPdisplay7  "PNP0907"       /* Western Digital VGA                   */
-#define PNPdisplay8  "PNP0908"       /* Western Digital Laptop VGA            */
-#define PNPdisplay9  "PNP0909"       /* S3                                    */
-#define PNPdisplayA  "PNP090A"       /* ATI Ultra Pro/Plus (Mach 32)          */
-#define PNPdisplayB  "PNP090B"       /* ATI Ultra (Mach 8)                    */
-#define PNPdisplayC  "PNP090C"       /* XGA Compatible                        */
-#define PNPdisplayD  "PNP090D"       /* ATI VGA Wonder                        */
-#define PNPdisplayE  "PNP090E"       /* Weitek P9000 Graphics Adapter         */
-#define PNPdisplayF  "PNP090F"       /* Oak Technology VGA                    */
-
-/* Peripheral busses */
-
-#define PNPbuses0    "PNP0A00"       /* ISA Bus                               */
-#define PNPbuses1    "PNP0A01"       /* EISA Bus                              */
-#define PNPbuses2    "PNP0A02"       /* MCA Bus                               */
-#define PNPbuses3    "PNP0A03"       /* PCI Bus                               */
-#define PNPbuses4    "PNP0A04"       /* VESA/VL Bus                           */
-
-/* RTC, BIOS, planar devices */
-
-#define PNPspeaker0  "PNP0800"       /* AT Style Speaker Sound                */
-#define PNPrtc0      "PNP0B00"       /* AT RTC                                */
-#define PNPpnpbios0  "PNP0C00"       /* PNP BIOS (only created by root enum)  */
-#define PNPpnpbios1  "PNP0C01"       /* System Board Memory Device            */
-#define PNPpnpbios2  "PNP0C02"       /* Math Coprocessor                      */
-#define PNPpnpbios3  "PNP0C03"       /* PNP BIOS Event Notification Interrupt */
-
-/* PCMCIA controller */
-
-#define PNPpcmcia0   "PNP0E00"       /* Intel 82365 Compatible PCMCIA Cntlr   */
-
-/* Mice */
-
-#define PNPmouse0    "PNP0F00"       /* Microsoft Bus Mouse                   */
-#define PNPmouse1    "PNP0F01"       /* Microsoft Serial Mouse                */
-#define PNPmouse2    "PNP0F02"       /* Microsoft Inport Mouse                */
-#define PNPmouse3    "PNP0F03"       /* Microsoft PS/2 Mouse                  */
-#define PNPmouse4    "PNP0F04"       /* Mousesystems Mouse                    */
-#define PNPmouse5    "PNP0F05"       /* Mousesystems 3 Button Mouse - COM2    */
-#define PNPmouse6    "PNP0F06"       /* Genius Mouse - COM1                   */
-#define PNPmouse7    "PNP0F07"       /* Genius Mouse - COM2                   */
-#define PNPmouse8    "PNP0F08"       /* Logitech Serial Mouse                 */
-#define PNPmouse9    "PNP0F09"       /* Microsoft Ballpoint Serial Mouse      */
-#define PNPmouseA    "PNP0F0A"       /* Microsoft PNP Mouse                   */
-#define PNPmouseB    "PNP0F0B"       /* Microsoft PNP Ballpoint Mouse         */
-
-/* Modems */
-
-#define PNPmodem0    "PNP9000"       /* Specific IDs TBD                      */
-
-/* Network controllers */
-
-#define PNPnetworkC9 "PNP80C9"       /* IBM Token Ring                        */
-#define PNPnetworkCA "PNP80CA"       /* IBM Token Ring II                     */
-#define PNPnetworkCB "PNP80CB"       /* IBM Token Ring II/Short               */
-#define PNPnetworkCC "PNP80CC"       /* IBM Token Ring 4/16Mbs                */
-#define PNPnetwork27 "PNP8327"       /* IBM Token Ring (All types)            */
-#define PNPnetworket "IBM0010"       /* IBM Ethernet used by Power PC         */
-#define PNPneteisaet "IBM2001"       /* IBM Ethernet EISA adapter             */
-#define PNPAMD79C970 "IBM0016"       /* AMD 79C970 (PCI Ethernet)             */
-
-/* SCSI controllers */
-
-#define PNPscsi0     "PNPA000"       /* Adaptec 154x Compatible SCSI Cntlr    */
-#define PNPscsi1     "PNPA001"       /* Adaptec 174x Compatible SCSI Cntlr    */
-#define PNPscsi2     "PNPA002"       /* Future Domain 16-700 Compat SCSI Cntlr*/
-#define PNPscsi3     "PNPA003"       /* Panasonic CDROM Adapter (SBPro/SB16)  */
-#define PNPscsiF     "IBM000F"       /* NCR 810 SCSI Controller               */
-#define PNPscsi825   "IBM001B"       /* NCR 825 SCSI Controller               */
-#define PNPscsi875   "IBM0018"       /* NCR 875 SCSI Controller               */
-
-/* Sound/Video, Multimedia */
-
-#define PNPmm0       "PNPB000"       /* Sound Blaster Compatible Sound Device */
-#define PNPmm1       "PNPB001"       /* MS Windows Sound System Compat Device */
-#define PNPmmF       "IBM000E"       /* Crystal CS4231 Audio Device           */
-#define PNPv7310     "IBM0015"       /* ASCII V7310 Video Capture Device      */
-#define PNPmm4232    "IBM0017"       /* Crystal CS4232 Audio Device           */
-#define PNPpmsyn     "IBM001D"       /* YMF 289B chip (Yamaha)                */
-#define PNPgp4232    "IBM0012"       /* Crystal CS4232 Game Port              */
-#define PNPmidi4232  "IBM0013"       /* Crystal CS4232 MIDI                   */
-
-/* Operator Panel */
-#define PNPopctl     "IBM000B"       /* Operator's panel                      */
-
-/* Service Processor */
-#define PNPsp        "IBM0011"       /* IBM Service Processor                 */
-#define PNPLTsp      "IBM001E"       /* Lightning/Terlingua Support Processor */
-#define PNPLTmsp     "IBM001F"       /* Lightning/Terlingua Mini-SP           */
-
-/* Memory Controller */
-#define PNPmemctl    "IBM000A"       /* Memory controller                     */
-
-/* Graphics Assist */
-#define PNPg_assist  "IBM0014"       /* Graphics Assist                       */
-
-/* Miscellaneous Device Controllers */
-#define PNPtablet    "IBM0019"       /* IBM Tablet Controller                 */
-
-/* PNP Packet Handles */
-
-#define S1_Packet                0x0A   /* Version resource                   */
-#define S2_Packet                0x15   /* Logical DEVID (without flags)      */
-#define S2_Packet_flags          0x16   /* Logical DEVID (with flags)         */
-#define S3_Packet                0x1C   /* Compatible device ID               */
-#define S4_Packet                0x22   /* IRQ resource (without flags)       */
-#define S4_Packet_flags          0x23   /* IRQ resource (with flags)          */
-#define S5_Packet                0x2A   /* DMA resource                       */
-#define S6_Packet                0x30   /* Depend funct start (w/o priority)  */
-#define S6_Packet_priority       0x31   /* Depend funct start (w/ priority)   */
-#define S7_Packet                0x38   /* Depend funct end                   */
-#define S8_Packet                0x47   /* I/O port resource (w/o fixed loc)  */
-#define S9_Packet_fixed          0x4B   /* I/O port resource (w/ fixed loc)   */
-#define S14_Packet               0x71   /* Vendor defined                     */
-#define S15_Packet               0x78   /* End of resource (w/o checksum)     */
-#define S15_Packet_checksum      0x79   /* End of resource (w/ checksum)      */
-#define L1_Packet                0x81   /* Memory range                       */
-#define L1_Shadow                0x20   /* Memory is shadowable               */
-#define L1_32bit_mem             0x18   /* 32-bit memory only                 */
-#define L1_8_16bit_mem           0x10   /* 8- and 16-bit supported            */
-#define L1_Decode_Hi             0x04   /* decode supports high address       */
-#define L1_Cache                 0x02   /* read cacheable, write-through      */
-#define L1_Writeable             0x01   /* Memory is writeable                */
-#define L2_Packet                0x82   /* ANSI ID string                     */
-#define L3_Packet                0x83   /* Unicode ID string                  */
-#define L4_Packet                0x84   /* Vendor defined                     */
-#define L5_Packet                0x85   /* Large I/O                          */
-#define L6_Packet                0x86   /* 32-bit Fixed Loc Mem Range Desc    */
-#define END_TAG                  0x78   /* End of resource                    */
-#define DF_START_TAG             0x30   /* Dependent function start           */
-#define DF_START_TAG_priority    0x31   /* Dependent function start           */
-#define DF_END_TAG               0x38   /* Dependent function end             */
-#define SUBOPTIMAL_CONFIGURATION 0x2    /* Priority byte sub optimal config   */
-
-/* Device Base Type Codes */
-
-typedef enum _PnP_BASE_TYPE {
-  Reserved = 0,
-  MassStorageDevice = 1,
-  NetworkInterfaceController = 2,
-  DisplayController = 3,
-  MultimediaController = 4,
-  MemoryController = 5,
-  BridgeController = 6,
-  CommunicationsDevice = 7,
-  SystemPeripheral = 8,
-  InputDevice = 9,
-  ServiceProcessor = 0x0A,              /* 11/2/95                            */
-  } PnP_BASE_TYPE;
-
-/* Device Sub Type Codes */
-
-typedef enum _PnP_SUB_TYPE {
-  SCSIController = 0,
-  IDEController = 1,
-  FloppyController = 2,
-  IPIController = 3,
-  OtherMassStorageController = 0x80,
-
-  EthernetController = 0,
-  TokenRingController = 1,
-  FDDIController = 2,
-  OtherNetworkController = 0x80,
-
-  VGAController= 0,
-  SVGAController= 1,
-  XGAController= 2,
-  OtherDisplayController = 0x80,
-
-  VideoController = 0,
-  AudioController = 1,
-  OtherMultimediaController = 0x80,
-
-  RAM = 0,
-  FLASH = 1,
-  OtherMemoryDevice = 0x80,
-
-  HostProcessorBridge = 0,
-  ISABridge = 1,
-  EISABridge = 2,
-  MicroChannelBridge = 3,
-  PCIBridge = 4,
-  PCMCIABridge = 5,
-  VMEBridge = 6,
-  OtherBridgeDevice = 0x80,
-
-  RS232Device = 0,
-  ATCompatibleParallelPort = 1,
-  OtherCommunicationsDevice = 0x80,
-
-  ProgrammableInterruptController = 0,
-  DMAController = 1,
-  SystemTimer = 2,
-  RealTimeClock = 3,
-  L2Cache = 4,
-  NVRAM = 5,
-  PowerManagement = 6,
-  CMOS = 7,
-  OperatorPanel = 8,
-  ServiceProcessorClass1 = 9,
-  ServiceProcessorClass2 = 0xA,
-  ServiceProcessorClass3 = 0xB,
-  GraphicAssist = 0xC,
-  SystemPlanar = 0xF,                   /* 10/5/95                            */
-  OtherSystemPeripheral = 0x80,
-
-  KeyboardController = 0,
-  Digitizer = 1,
-  MouseController = 2,
-  TabletController = 3,                 /* 10/27/95                           */
-  OtherInputController = 0x80,
-
-  GeneralMemoryController = 0,
-  } PnP_SUB_TYPE;
-
-/* Device Interface Type Codes */
-
-typedef enum _PnP_INTERFACE {
-  General = 0,
-  GeneralSCSI = 0,
-  GeneralIDE = 0,
-  ATACompatible = 1,
-
-  GeneralFloppy = 0,
-  Compatible765 = 1,
-  NS398_Floppy = 2,                     /* NS Super I/O wired to use index
-					   register at port 398 and data
-					   register at port 399               */
-  NS26E_Floppy = 3,                     /* Ports 26E and 26F                  */
-  NS15C_Floppy = 4,                     /* Ports 15C and 15D                  */
-  NS2E_Floppy = 5,                      /* Ports 2E and 2F                    */
-  CHRP_Floppy = 6,                      /* CHRP Floppy in PR*P system         */
-
-  GeneralIPI = 0,
-
-  GeneralEther = 0,
-  GeneralToken = 0,
-  GeneralFDDI = 0,
-
-  GeneralVGA = 0,
-  GeneralSVGA = 0,
-  GeneralXGA = 0,
-
-  GeneralVideo = 0,
-  GeneralAudio = 0,
-  CS4232Audio = 1,                      /* CS 4232 Plug 'n Play Configured    */
-
-  GeneralRAM = 0,
-  GeneralFLASH = 0,
-  PCIMemoryController = 0,              /* PCI Config Method                  */
-  RS6KMemoryController = 1,             /* RS6K Config Method                 */
-
-  GeneralHostBridge = 0,
-  GeneralISABridge = 0,
-  GeneralEISABridge = 0,
-  GeneralMCABridge = 0,
-  GeneralPCIBridge = 0,
-  PCIBridgeDirect = 0,
-  PCIBridgeIndirect = 1,
-  PCIBridgeRS6K = 2,
-  GeneralPCMCIABridge = 0,
-  GeneralVMEBridge = 0,
-
-  GeneralRS232 = 0,
-  COMx = 1,
-  Compatible16450 = 2,
-  Compatible16550 = 3,
-  NS398SerPort = 4,                     /* NS Super I/O wired to use index
-					   register at port 398 and data
-					   register at port 399               */
-  NS26ESerPort = 5,                     /* Ports 26E and 26F                  */
-  NS15CSerPort = 6,                     /* Ports 15C and 15D                  */
-  NS2ESerPort = 7,                      /* Ports 2E and 2F                    */
-
-  GeneralParPort = 0,
-  LPTx = 1,
-  NS398ParPort = 2,                     /* NS Super I/O wired to use index
-					   register at port 398 and data
-					   register at port 399               */
-  NS26EParPort = 3,                     /* Ports 26E and 26F                  */
-  NS15CParPort = 4,                     /* Ports 15C and 15D                  */
-  NS2EParPort = 5,                      /* Ports 2E and 2F                    */
-
-  GeneralPIC = 0,
-  ISA_PIC = 1,
-  EISA_PIC = 2,
-  MPIC = 3,
-  RS6K_PIC = 4,
-
-  GeneralDMA = 0,
-  ISA_DMA = 1,
-  EISA_DMA = 2,
-
-  GeneralTimer = 0,
-  ISA_Timer = 1,
-  EISA_Timer = 2,
-  GeneralRTC = 0,
-  ISA_RTC = 1,
-
-  StoreThruOnly = 1,
-  StoreInEnabled = 2,
-  RS6KL2Cache = 3,
-
-  IndirectNVRAM = 0,                    /* Indirectly addressed               */
-  DirectNVRAM = 1,                      /* Memory Mapped                      */
-  IndirectNVRAM24 = 2,                  /* Indirectly addressed - 24 bit      */
-
-  GeneralPowerManagement = 0,
-  EPOWPowerManagement = 1,
-  PowerControl = 2,                    /* d1378 */
-
-  GeneralCMOS = 0,
-
-  GeneralOPPanel = 0,
-  HarddiskLight = 1,
-  CDROMLight = 2,
-  PowerLight = 3,
-  KeyLock = 4,
-  ANDisplay = 5,                        /* AlphaNumeric Display               */
-  SystemStatusLED = 6,                  /* 3 digit 7 segment LED              */
-  CHRP_SystemStatusLED = 7,             /* CHRP LEDs in PR*P system           */
-
-  GeneralServiceProcessor = 0,
-
-  TransferData = 1,
-  IGMC32 = 2,
-  IGMC64 = 3,
-
-  GeneralSystemPlanar = 0,              /* 10/5/95                            */
-
-  } PnP_INTERFACE;
-
-/* PnP resources */
-
-/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */
-
-typedef struct _SERIAL_ID {
-  unsigned char VendorID0;              /*    Bit(7)=0                        */
-					/*    Bits(6:2)=1st character in      */
-					/*       compressed ASCII             */
-					/*    Bits(1:0)=2nd character in      */
-					/*       compressed ASCII bits(4:3)   */
-  unsigned char VendorID1;              /*    Bits(7:5)=2nd character in      */
-					/*       compressed ASCII bits(2:0)   */
-					/*    Bits(4:0)=3rd character in      */
-					/*       compressed ASCII             */
-  unsigned char VendorID2;              /* Product number - vendor assigned   */
-  unsigned char VendorID3;              /* Product number - vendor assigned   */
-
-/* Serial number is to provide uniqueness if more than one board of same      */
-/* type is in system.  Must be "FFFFFFFF" if feature not supported.           */
-
-  unsigned char Serial0;                /* Unique serial number bits (7:0)    */
-  unsigned char Serial1;                /* Unique serial number bits (15:8)   */
-  unsigned char Serial2;                /* Unique serial number bits (23:16)  */
-  unsigned char Serial3;                /* Unique serial number bits (31:24)  */
-  unsigned char Checksum;
-  } SERIAL_ID;
-
-typedef enum _PnPItemName {
-  Unused = 0,
-  PnPVersion = 1,
-  LogicalDevice = 2,
-  CompatibleDevice = 3,
-  IRQFormat = 4,
-  DMAFormat = 5,
-  StartDepFunc = 6,
-  EndDepFunc = 7,
-  IOPort = 8,
-  FixedIOPort = 9,
-  Res1 = 10,
-  Res2 = 11,
-  Res3 = 12,
-  SmallVendorItem = 14,
-  EndTag = 15,
-  MemoryRange = 1,
-  ANSIIdentifier = 2,
-  UnicodeIdentifier = 3,
-  LargeVendorItem = 4,
-  MemoryRange32 = 5,
-  MemoryRangeFixed32 = 6,
-  } PnPItemName;
-
-/* Define a bunch of access functions for the bits in the tag field */
-
-/* Tag type - 0 = small; 1 = large */
-#define tag_type(t) (((t) & 0x80)>>7)
-#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7))
-
-/* Small item name is 4 bits - one of PnPItemName enum above */
-#define tag_small_item_name(t) (((t) & 0x78)>>3)
-#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3))
-
-/* Small item count is 3 bits - count of further bytes in packet */
-#define tag_small_count(t) ((t) & 0x07)
-#define set_tag_count(t,v) (t = (t & 0x78) | (v))
-
-/* Large item name is 7 bits - one of PnPItemName enum above */
-#define tag_large_item_name(t) ((t) & 0x7f)
-#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v))
-
-/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */
-
-typedef union _PnP_TAG_PACKET {
-  struct _S1_Pack{                      /* VERSION PACKET                     */
-    unsigned char Tag;                  /* small tag = 0x0a                   */
-    unsigned char Version[2];           /* PnP version, Vendor version        */
-    } S1_Pack;
-
-  struct _S2_Pack{                      /* LOGICAL DEVICE ID PACKET           */
-    unsigned char Tag;                  /* small tag = 0x15 or 0x16           */
-    unsigned char DevId[4];             /* Logical device id                  */
-    unsigned char Flags[2];             /* bit(0) boot device;                */
-					/* bit(7:1) cmd in range x31-x37      */
-					/* bit(7:0) cmd in range x28-x3f (opt)*/
-    } S2_Pack;
-
-  struct _S3_Pack{                      /* COMPATIBLE DEVICE ID PACKET        */
-    unsigned char Tag;                  /* small tag = 0x1c                   */
-    unsigned char CompatId[4];          /* Compatible device id               */
-    } S3_Pack;
-
-  struct _S4_Pack{                      /* IRQ PACKET                         */
-    unsigned char Tag;                  /* small tag = 0x22 or 0x23           */
-    unsigned char IRQMask[2];           /* bit(0) is IRQ0, ...;               */
-					/* bit(0) is IRQ8 ...                 */
-    unsigned char IRQInfo;              /* optional; assume bit(0)=1; else    */
-					/*  bit(0) - high true edge sensitive */
-					/*  bit(1) - low true edge sensitive  */
-					/*  bit(2) - high true level sensitive*/
-					/*  bit(3) - low true level sensitive */
-					/*  bit(7:4) - must be 0              */
-    } S4_Pack;
-
-  struct _S5_Pack{                      /* DMA PACKET                         */
-    unsigned char Tag;                  /* small tag = 0x2a                   */
-    unsigned char DMAMask;              /* bit(0) is channel 0 ...            */
-    unsigned char DMAInfo;
-    } S5_Pack;
-
-  struct _S6_Pack{                      /* START DEPENDENT FUNCTION PACKET    */
-    unsigned char Tag;                  /* small tag = 0x30 or 0x31           */
-    unsigned char Priority;             /* Optional; if missing then x01; else*/
-					/*  x00 = best possible               */
-					/*  x01 = acceptible                  */
-					/*  x02 = sub-optimal but functional  */
-    } S6_Pack;
-
-  struct _S7_Pack{                      /* END DEPENDENT FUNCTION PACKET      */
-    unsigned char Tag;                  /* small tag = 0x38                   */
-    } S7_Pack;
-
-  struct _S8_Pack{                      /* VARIABLE I/O PORT PACKET           */
-    unsigned char Tag;                  /* small tag x47                      */
-    unsigned char IOInfo;               /* x0  = decode only bits(9:0);       */
-#define  ISAAddr16bit         0x01      /* x01 = decode bits(15:0)            */
-    unsigned char RangeMin[2];          /* Min base address                   */
-    unsigned char RangeMax[2];          /* Max base address                   */
-    unsigned char IOAlign;              /* base alignmt, incr in 1B blocks    */
-    unsigned char IONum;                /* number of contiguous I/O ports     */
-    } S8_Pack;
-
-  struct _S9_Pack{                      /* FIXED I/O PORT PACKET              */
-    unsigned char Tag;                  /* small tag = 0x4b                   */
-    unsigned char Range[2];             /* base address 10 bits               */
-    unsigned char IONum;                /* number of contiguous I/O ports     */
-    } S9_Pack;
-
-  struct _S14_Pack{                     /* VENDOR DEFINED PACKET              */
-    unsigned char Tag;                  /* small tag = 0x7m m = 1-7           */
-    union _S14_Data{
-      unsigned char Data[7];            /* Vendor defined                     */
-      struct _S14_PPCPack{              /* Pr*p s14 pack                      */
-	 unsigned char Type;            /* 00=non-IBM                         */
-	 unsigned char PPCData[6];      /* Vendor defined                     */
-	} S14_PPCPack;
-      } S14_Data;
-    } S14_Pack;
-
-  struct _S15_Pack{                     /* END PACKET                         */
-    unsigned char Tag;                  /* small tag = 0x78 or 0x79           */
-    unsigned char Check;                /* optional - checksum                */
-    } S15_Pack;
-
-  struct _L1_Pack{                      /* MEMORY RANGE PACKET                */
-    unsigned char Tag;                  /* large tag = 0x81                   */
-    unsigned char Count0;               /* x09                                */
-    unsigned char Count1;               /* x00                                */
-    unsigned char Data[9];              /* a variable array of bytes,         */
-					/* count in tag                       */
-    } L1_Pack;
-
-  struct _L2_Pack{                      /* ANSI ID STRING PACKET              */
-    unsigned char Tag;                  /* large tag = 0x82                   */
-    unsigned char Count0;               /* Length of string                   */
-    unsigned char Count1;
-    unsigned char Identifier[1];        /* a variable array of bytes,         */
-					/* count in tag                       */
-    } L2_Pack;
-
-  struct _L3_Pack{                      /* UNICODE ID STRING PACKET           */
-    unsigned char Tag;                  /* large tag = 0x83                   */
-    unsigned char Count0;               /* Length + 2 of string               */
-    unsigned char Count1;
-    unsigned char Country0;             /* TBD                                */
-    unsigned char Country1;             /* TBD                                */
-    unsigned char Identifier[1];        /* a variable array of bytes,         */
-					/* count in tag                       */
-    } L3_Pack;
-
-  struct _L4_Pack{                      /* VENDOR DEFINED PACKET              */
-    unsigned char Tag;                  /* large tag = 0x84                   */
-    unsigned char Count0;
-    unsigned char Count1;
-    union _L4_Data{
-      unsigned char Data[1];            /* a variable array of bytes,         */
-					/* count in tag                       */
-      struct _L4_PPCPack{               /* Pr*p L4 packet                     */
-	 unsigned char Type;            /* 00=non-IBM                         */
-	 unsigned char PPCData[1];      /* a variable array of bytes,         */
-					/* count in tag                       */
-	} L4_PPCPack;
-      } L4_Data;
-    } L4_Pack;
-
-  struct _L5_Pack{
-    unsigned char Tag;                  /* large tag = 0x85                   */
-    unsigned char Count0;               /* Count = 17                         */
-    unsigned char Count1;
-    unsigned char Data[17];
-    } L5_Pack;
-
-  struct _L6_Pack{
-    unsigned char Tag;                  /* large tag = 0x86                   */
-    unsigned char Count0;               /* Count = 9                          */
-    unsigned char Count1;
-    unsigned char Data[9];
-    } L6_Pack;
-
-  } PnP_TAG_PACKET;
-
-#endif /* __ASSEMBLY__ */
-#endif  /* ndef _PNP_ */
diff --git a/arch/powerpc/include/asm/residual.h b/arch/powerpc/include/asm/residual.h
deleted file mode 100644
index dc85edbc3c..0000000000
--- a/arch/powerpc/include/asm/residual.h
+++ /dev/null
@@ -1,331 +0,0 @@
-/* 7/18/95                                                                    */
-/*----------------------------------------------------------------------------*/
-/*      Residual Data header definitions and prototypes                       */
-/*----------------------------------------------------------------------------*/
-
-/* Structure map for RESIDUAL on PowerPC Reference Platform                   */
-/* residual.h - Residual data structure passed in r3.                         */
-/*              Load point passed in r4 to boot image.                        */
-/* For enum's: if given in hex then they are bit significant,                 */
-/*             i.e. only one bit is on for each enum                          */
-/* Reserved fields must be filled with zeros.                                */
-
-#ifndef _RESIDUAL_
-#define _RESIDUAL_
-
-#ifndef __ASSEMBLY__
-
-#define MAX_CPUS 32                     /* These should be set to the maximum */
-#define MAX_MEMS 64                     /* number possible for this system.   */
-#define MAX_DEVICES 256                 /* Changing these will change the     */
-#define AVE_PNP_SIZE 32                 /* structure, hence the version of    */
-#define MAX_MEM_SEGS 64                 /* this header file.                  */
-
-/*----------------------------------------------------------------------------*/
-/*               Public structures...                                         */
-/*----------------------------------------------------------------------------*/
-
-#include "pnp.h"
-
-typedef enum _L1CACHE_TYPE {
-  NoneCAC = 0,
-  SplitCAC = 1,
-  CombinedCAC = 2
-  } L1CACHE_TYPE;
-
-typedef enum _TLB_TYPE {
-  NoneTLB = 0,
-  SplitTLB = 1,
-  CombinedTLB = 2
-  } TLB_TYPE;
-
-typedef enum _FIRMWARE_SUPPORT {
-  Conventional = 0x01,
-  OpenFirmware = 0x02,
-  Diagnostics = 0x04,
-  LowDebug = 0x08,
-  Multiboot = 0x10,
-  LowClient = 0x20,
-  Hex41 = 0x40,
-  FAT = 0x80,
-  ISO9660 = 0x0100,
-  SCSI_InitiatorID_Override = 0x0200,
-  Tape_Boot = 0x0400,
-  FW_Boot_Path = 0x0800
-  } FIRMWARE_SUPPORT;
-
-typedef enum _FIRMWARE_SUPPLIERS {
-  IBMFirmware = 0x00,
-  MotoFirmware = 0x01,                  /* 7/18/95                            */
-  FirmWorks = 0x02,                     /* 10/5/95                            */
-  Bull = 0x03,                          /* 04/03/96                           */
-  } FIRMWARE_SUPPLIERS;
-
-typedef enum _ENDIAN_SWITCH_METHODS {
-  UsePort92 = 0x01,
-  UsePCIConfigA8 = 0x02,
-  UseFF001030 = 0x03,
-  } ENDIAN_SWITCH_METHODS;
-
-typedef enum _SPREAD_IO_METHODS {
-  UsePort850 = 0x00,
-/*UsePCIConfigA8 = 0x02,*/
-  } SPREAD_IO_METHODS;
-
-typedef struct _VPD {
-
-  /* Box dependent stuff */
-  unsigned char PrintableModel[32];     /* Null terminated string.
-					   Must be of the form:
-					   vvv,<20h>,<model designation>,<0x0>
-					   where vvv is the vendor ID
-					   e.g. IBM PPS MODEL 6015<0x0>       */
-  unsigned char Serial[16];             /* 12/94:
-					   Serial Number; must be of the form:
-					   vvv<serial number> where vvv is the
-					   vendor ID.
-					   e.g. IBM60151234567<20h><20h>      */
-  unsigned char Reserved[48];
-  unsigned long FirmwareSupplier;       /* See FirmwareSuppliers enum         */
-  unsigned long FirmwareSupports;       /* See FirmwareSupport enum           */
-  unsigned long NvramSize;              /* Size of nvram in bytes             */
-  unsigned long NumSIMMSlots;
-  unsigned short EndianSwitchMethod;    /* See EndianSwitchMethods enum       */
-  unsigned short SpreadIOMethod;        /* See SpreadIOMethods enum           */
-  unsigned long SmpIar;
-  unsigned long RAMErrLogOffset;        /* Heap offset to error log           */
-  unsigned long Reserved5;
-  unsigned long Reserved6;
-  unsigned long ProcessorHz;            /* Processor clock frequency in Hertz */
-  unsigned long ProcessorBusHz;         /* Processor bus clock frequency      */
-  unsigned long Reserved7;
-  unsigned long TimeBaseDivisor;        /* (Bus clocks per timebase tic)*1000 */
-  unsigned long WordWidth;              /* Word width in bits                 */
-  unsigned long PageSize;               /* Page size in bytes                 */
-  unsigned long CoherenceBlockSize;     /* Unit of transfer in/out of cache
-					   for which coherency is maintained;
-					   normally <= CacheLineSize.         */
-  unsigned long GranuleSize;            /* Unit of lock allocation to avoid   */
-					/*   false sharing of locks.          */
-
-  /* L1 Cache variables */
-  unsigned long CacheSize;              /* L1 Cache size in KB. This is the   */
-					/*   total size of the L1, whether    */
-					/*   combined or split                */
-  unsigned long CacheAttrib;            /* L1CACHE_TYPE                       */
-  unsigned long CacheAssoc;             /* L1 Cache associativity. Use this
-					   for combined cache. If split, put
-					   zeros here.                        */
-  unsigned long CacheLineSize;          /* L1 Cache line size in bytes. Use
-					   for combined cache. If split, put
-					   zeros here.                        */
-  /* For split L1 Cache: (= combined if combined cache) */
-  unsigned long I_CacheSize;
-  unsigned long I_CacheAssoc;
-  unsigned long I_CacheLineSize;
-  unsigned long D_CacheSize;
-  unsigned long D_CacheAssoc;
-  unsigned long D_CacheLineSize;
-
-  /* Translation Lookaside Buffer variables */
-  unsigned long TLBSize;                /* Total number of TLBs on the system */
-  unsigned long TLBAttrib;              /* Combined I+D or split TLB          */
-  unsigned long TLBAssoc;               /* TLB Associativity. Use this for
-					   combined TLB. If split, put zeros
-					   here.                              */
-  /* For split TLB: (= combined if combined TLB) */
-  unsigned long I_TLBSize;
-  unsigned long I_TLBAssoc;
-  unsigned long D_TLBSize;
-  unsigned long D_TLBAssoc;
-
-  unsigned long ExtendedVPD;            /* Offset to extended VPD area;
-					   null if unused                     */
-  } VPD;
-
-typedef enum _DEVICE_FLAGS {
-  Enabled = 0x4000,                     /* 1 - PCI device is enabled          */
-  Integrated = 0x2000,
-  Failed = 0x1000,                      /* 1 - device failed POST code tests  */
-  Static = 0x0800,                      /* 0 - dynamically configurable
-					   1 - static                         */
-  Dock = 0x0400,                        /* 0 - not a docking station device
-					   1 - is a docking station device    */
-  Boot = 0x0200,                        /* 0 - device cannot be used for BOOT
-					   1 - can be a BOOT device           */
-  Configurable = 0x0100,                /* 1 - device is configurable         */
-  Disableable = 0x80,                   /* 1 - device can be disabled         */
-  PowerManaged = 0x40,                  /* 0 - not managed; 1 - managed       */
-  ReadOnly = 0x20,                      /* 1 - device is read only            */
-  Removable = 0x10,                     /* 1 - device is removable            */
-  ConsoleIn = 0x08,
-  ConsoleOut = 0x04,
-  Input = 0x02,
-  Output = 0x01
-  } DEVICE_FLAGS;
-
-typedef enum _BUS_ID {
-  ISADEVICE = 0x01,
-  EISADEVICE = 0x02,
-  PCIDEVICE = 0x04,
-  PCMCIADEVICE = 0x08,
-  PNPISADEVICE = 0x10,
-  MCADEVICE = 0x20,
-  MXDEVICE = 0x40,                      /* Devices on mezzanine bus           */
-  PROCESSORDEVICE = 0x80,               /* Devices on processor bus           */
-  VMEDEVICE = 0x100,
-  } BUS_ID;
-
-typedef struct _DEVICE_ID {
-  unsigned long BusId;                  /* See BUS_ID enum above              */
-  unsigned long DevId;                  /* Big Endian format                  */
-  unsigned long SerialNum;              /* For multiple usage of a single
-					   DevId                              */
-  unsigned long Flags;                  /* See DEVICE_FLAGS enum above        */
-  unsigned char BaseType;               /* See pnp.h for bit definitions      */
-  unsigned char SubType;                /* See pnp.h for bit definitions      */
-  unsigned char Interface;              /* See pnp.h for bit definitions      */
-  unsigned char Spare;
-  } DEVICE_ID;
-
-typedef union _BUS_ACCESS {
-  struct _PnPAccess{
-    unsigned char CSN;
-    unsigned char LogicalDevNumber;
-    unsigned short ReadDataPort;
-    } PnPAccess;
-  struct _ISAAccess{
-    unsigned char SlotNumber;           /* ISA Slot Number generally not
-					   available; 0 if unknown            */
-    unsigned char LogicalDevNumber;
-    unsigned short ISAReserved;
-    } ISAAccess;
-  struct _MCAAccess{
-    unsigned char SlotNumber;
-    unsigned char LogicalDevNumber;
-    unsigned short MCAReserved;
-    } MCAAccess;
-  struct _PCMCIAAccess{
-    unsigned char SlotNumber;
-    unsigned char LogicalDevNumber;
-    unsigned short PCMCIAReserved;
-    } PCMCIAAccess;
-  struct _EISAAccess{
-    unsigned char SlotNumber;
-    unsigned char FunctionNumber;
-    unsigned short EISAReserved;
-    } EISAAccess;
-  struct _PCIAccess{
-    unsigned char BusNumber;
-    unsigned char DevFuncNumber;
-    unsigned short PCIReserved;
-    } PCIAccess;
-  struct _ProcBusAccess{
-    unsigned char BusNumber;
-    unsigned char BUID;
-    unsigned short ProcBusReserved;
-    } ProcBusAccess;
-  } BUS_ACCESS;
-
-/* Per logical device information */
-typedef struct _PPC_DEVICE {
-  DEVICE_ID DeviceId;
-  BUS_ACCESS BusAccess;
-
-  /* The following three are offsets into the DevicePnPHeap */
-  /* All are in PnP compressed format                       */
-  unsigned long AllocatedOffset;        /* Allocated resource description     */
-  unsigned long PossibleOffset;         /* Possible resource description      */
-  unsigned long CompatibleOffset;       /* Compatible device identifiers      */
-  } PPC_DEVICE;
-
-typedef enum _CPU_STATE {
-  CPU_GOOD = 0,                         /* CPU is present, and active         */
-  CPU_GOOD_FW = 1,                      /* CPU is present, and in firmware    */
-  CPU_OFF = 2,                          /* CPU is present, but inactive       */
-  CPU_FAILED = 3,                       /* CPU is present, but failed POST    */
-  CPU_NOT_PRESENT = 255                 /* CPU not present                    */
-  } CPU_STATE;
-
-typedef struct _PPC_CPU {
-  unsigned long CpuType;                /* Result of mfspr from Processor
-					   Version Register (PVR).
-					   PVR(0-15) = Version (e.g. 601)
-					   PVR(16-31 = EC Level               */
-  unsigned char CpuNumber;              /* CPU Number for this processor      */
-  unsigned char CpuState;               /* CPU State, see CPU_STATE enum      */
-  unsigned short Reserved;
-  } PPC_CPU;
-
-typedef struct _PPC_MEM {
-  unsigned long SIMMSize;               /* 0 - absent or bad
-					   8M, 32M (in MB)                    */
-  } PPC_MEM;
-
-typedef enum _MEM_USAGE {
-  Other = 0x8000,
-  ResumeBlock = 0x4000,                 /* for use by power management        */
-  SystemROM = 0x2000,                   /* Flash memory (populated)           */
-  UnPopSystemROM = 0x1000,              /* Unpopulated part of SystemROM area */
-  IOMemory = 0x0800,
-  SystemIO = 0x0400,
-  SystemRegs = 0x0200,
-  PCIAddr = 0x0100,
-  PCIConfig = 0x80,
-  ISAAddr = 0x40,
-  Unpopulated = 0x20,                   /* Unpopulated part of System Memory  */
-  Free = 0x10,                          /* Free part of System Memory         */
-  BootImage = 0x08,                     /* BootImage part of System Memory    */
-  FirmwareCode = 0x04,                  /* FirmwareCode part of System Memory */
-  FirmwareHeap = 0x02,                  /* FirmwareHeap part of System Memory */
-  FirmwareStack = 0x01                  /* FirmwareStack part of System Memory*/
-  } MEM_USAGE;
-
-typedef struct _MEM_MAP {
-  unsigned long Usage;                  /* See MEM_USAGE above                */
-  unsigned long BasePage;               /* Page number measured in 4KB pages  */
-  unsigned long PageCount;              /* Page count measured in 4KB pages   */
-  } MEM_MAP;
-
-typedef struct _RESIDUAL {
-  unsigned long ResidualLength;         /* Length of Residual                 */
-  unsigned char Version;                /* of this data structure             */
-  unsigned char Revision;               /* of this data structure             */
-  unsigned short EC;                    /* of this data structure             */
-  /* VPD */
-  VPD VitalProductData;
-  /* CPU */
-  unsigned short MaxNumCpus;            /* Max CPUs in this system            */
-  unsigned short ActualNumCpus;         /* ActualNumCpus < MaxNumCpus means   */
-					/* that there are unpopulated or      */
-					/* otherwise unusable cpu locations   */
-  PPC_CPU Cpus[MAX_CPUS];
-  /* Memory */
-  unsigned long TotalMemory;            /* Total amount of memory installed   */
-  unsigned long GoodMemory;             /* Total amount of good memory        */
-  unsigned long ActualNumMemSegs;
-  MEM_MAP Segs[MAX_MEM_SEGS];
-  unsigned long ActualNumMemories;
-  PPC_MEM Memories[MAX_MEMS];
-  /* Devices */
-  unsigned long ActualNumDevices;
-  PPC_DEVICE Devices[MAX_DEVICES];
-  unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE];
-  } RESIDUAL;
-
-
-extern RESIDUAL *res;
-extern void print_residual_device_info(void);
-extern PPC_DEVICE *residual_find_device(unsigned long BusMask,
-					unsigned char * DevID, int BaseType,
-					int SubType, int Interface, int n);
-extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag,
-				       int n);
-extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p,
-						    unsigned packet_type,
-						    int n);
-extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p,
-						    unsigned packet_type,
-						    int n);
-#endif /* __ASSEMBLY__ */
-#endif  /* ndef _RESIDUAL_ */
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 725b505177..2e2fc58a1b 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -143,7 +143,7 @@ void *os_malloc(size_t length)
 	return hdr + 1;
 }
 
-void *os_free(void *ptr)
+void os_free(void *ptr)
 {
 	struct os_mem_hdr *hdr = ptr;
 
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
deleted file mode 100644
index fac2e58502..0000000000
--- a/arch/x86/include/asm/mtrr.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * Generic MTRR (Memory Type Range Register) ioctls.
- * Taken from the Linux kernel
- *
- * (C) Copyright 2012
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * Copyright (C) 1997-1999  Richard Gooch <rgooch@atnf.csiro.au>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_X86_MTRR_H
-#define _ASM_X86_MTRR_H
-
-#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
-#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-#include <linux/ioctl.h>
-#include <errno.h>
-
-#define	MTRR_IOCTL_BASE	'M'
-
-struct mtrr_sentry {
-	unsigned long base;	/*  Base address     */
-	unsigned int size;	/*  Size of region   */
-	unsigned int type;	/*  Type of region   */
-};
-
-/*
- * Warning: this structure has a different order from i386
- * on x86-64. The 32bit emulation code takes care of that.
- * But you need to use this for 64bit, otherwise your X server
- * will break.
- */
-
-#ifdef __i386__
-struct mtrr_gentry {
-	unsigned int regnum;	/*  Register number  */
-	unsigned long base;	/*  Base address     */
-	unsigned int size;	/*  Size of region   */
-	unsigned int type;	/*  Type of region   */
-};
-
-#else /* __i386__ */
-
-struct mtrr_gentry {
-	unsigned long base;	/*  Base address     */
-	unsigned int size;	/*  Size of region   */
-	unsigned int regnum;	/*  Register number  */
-	unsigned int type;	/*  Type of region   */
-};
-#endif /* !__i386__ */
-
-struct mtrr_var_range {
-	__u32 base_lo;
-	__u32 base_hi;
-	__u32 mask_lo;
-	__u32 mask_hi;
-};
-
-/*
- * In the Intel processor's MTRR interface, the MTRR type is always held in
- * an 8 bit field:
- */
-typedef __u8 mtrr_type;
-
-#define MTRR_NUM_FIXED_RANGES 88
-#define MTRR_MAX_VAR_RANGES 256
-
-struct mtrr_state_type {
-	struct mtrr_var_range var_ranges[MTRR_MAX_VAR_RANGES];
-	mtrr_type fixed_ranges[MTRR_NUM_FIXED_RANGES];
-	unsigned char enabled;
-	unsigned char have_fixed;
-	mtrr_type def_type;
-};
-
-/*  These are the various ioctls  */
-#define MTRRIOC_ADD_ENTRY        _IOW(MTRR_IOCTL_BASE,  0, struct mtrr_sentry)
-#define MTRRIOC_SET_ENTRY        _IOW(MTRR_IOCTL_BASE,  1, struct mtrr_sentry)
-#define MTRRIOC_DEL_ENTRY        _IOW(MTRR_IOCTL_BASE,  2, struct mtrr_sentry)
-#define MTRRIOC_GET_ENTRY        _IOWR(MTRR_IOCTL_BASE, 3, struct mtrr_gentry)
-#define MTRRIOC_KILL_ENTRY       _IOW(MTRR_IOCTL_BASE,  4, struct mtrr_sentry)
-#define MTRRIOC_ADD_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  5, struct mtrr_sentry)
-#define MTRRIOC_SET_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  6, struct mtrr_sentry)
-#define MTRRIOC_DEL_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  7, struct mtrr_sentry)
-#define MTRRIOC_GET_PAGE_ENTRY   _IOWR(MTRR_IOCTL_BASE, 8, struct mtrr_gentry)
-#define MTRRIOC_KILL_PAGE_ENTRY  _IOW(MTRR_IOCTL_BASE,  9, struct mtrr_sentry)
-
-/*  These are the region types  */
-#define MTRR_TYPE_UNCACHABLE 0
-#define MTRR_TYPE_WRCOMB     1
-/*#define MTRR_TYPE_         2*/
-/*#define MTRR_TYPE_         3*/
-#define MTRR_TYPE_WRTHROUGH  4
-#define MTRR_TYPE_WRPROT     5
-#define MTRR_TYPE_WRBACK     6
-#define MTRR_NUM_TYPES       7
-
-#ifdef __KERNEL__
-
-/*  The following functions are for use by other drivers  */
-# ifdef CONFIG_MTRR
-extern u8 mtrr_type_lookup(u64 addr, u64 end);
-extern void mtrr_save_fixed_ranges(void *);
-extern void mtrr_save_state(void);
-extern int mtrr_add(unsigned long base, unsigned long size,
-		    unsigned int type, bool increment);
-extern int mtrr_add_page(unsigned long base, unsigned long size,
-			 unsigned int type, bool increment);
-extern int mtrr_del(int reg, unsigned long base, unsigned long size);
-extern int mtrr_del_page(int reg, unsigned long base, unsigned long size);
-extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi);
-extern void mtrr_ap_init(void);
-extern void mtrr_bp_init(void);
-extern void set_mtrr_aps_delayed_init(void);
-extern void mtrr_aps_init(void);
-extern void mtrr_bp_restore(void);
-extern int mtrr_trim_uncached_memory(unsigned long end_pfn);
-extern int amd_special_default_mtrr(void);
-#  else
-static inline u8 mtrr_type_lookup(u64 addr, u64 end)
-{
-	/*
-	 * Return no-MTRRs:
-	 */
-	return 0xff;
-}
-#define mtrr_save_fixed_ranges(arg) do {} while (0)
-#define mtrr_save_state() do {} while (0)
-static inline int mtrr_del(int reg, unsigned long base, unsigned long size)
-{
-	return -ENODEV;
-}
-static inline int mtrr_del_page(int reg, unsigned long base, unsigned long size)
-{
-	return -ENODEV;
-}
-static inline int mtrr_trim_uncached_memory(unsigned long end_pfn)
-{
-	return 0;
-}
-static inline void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi)
-{
-}
-
-#define mtrr_ap_init() do {} while (0)
-#define mtrr_bp_init() do {} while (0)
-#define set_mtrr_aps_delayed_init() do {} while (0)
-#define mtrr_aps_init() do {} while (0)
-#define mtrr_bp_restore() do {} while (0)
-#  endif
-
-#ifdef CONFIG_COMPAT
-#include <linux/compat.h>
-
-struct mtrr_sentry32 {
-	compat_ulong_t base;	/*  Base address     */
-	compat_uint_t size;	/*  Size of region   */
-	compat_uint_t type;	/*  Type of region   */
-};
-
-struct mtrr_gentry32 {
-	compat_ulong_t regnum;	/*  Register number  */
-	compat_uint_t base;	/*  Base address     */
-	compat_uint_t size;	/*  Size of region   */
-	compat_uint_t type;	/*  Type of region   */
-};
-
-#define MTRR_IOCTL_BASE 'M'
-
-#define MTRRIOC32_ADD_ENTRY      _IOW(MTRR_IOCTL_BASE,  0, struct mtrr_sentry32)
-#define MTRRIOC32_SET_ENTRY      _IOW(MTRR_IOCTL_BASE,  1, struct mtrr_sentry32)
-#define MTRRIOC32_DEL_ENTRY      _IOW(MTRR_IOCTL_BASE,  2, struct mtrr_sentry32)
-#define MTRRIOC32_GET_ENTRY      _IOWR(MTRR_IOCTL_BASE, 3, struct mtrr_gentry32)
-#define MTRRIOC32_KILL_ENTRY     _IOW(MTRR_IOCTL_BASE,  4, struct mtrr_sentry32)
-#define MTRRIOC32_ADD_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE,  5, struct mtrr_sentry32)
-#define MTRRIOC32_SET_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE,  6, struct mtrr_sentry32)
-#define MTRRIOC32_DEL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE,  7, struct mtrr_sentry32)
-#define MTRRIOC32_GET_PAGE_ENTRY _IOWR(MTRR_IOCTL_BASE, 8, struct mtrr_gentry32)
-#define MTRRIOC32_KILL_PAGE_ENTRY		\
-				 _IOW(MTRR_IOCTL_BASE,  9, struct mtrr_sentry32)
-#endif /* CONFIG_COMPAT */
-
-#endif /* __KERNEL__ */
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_X86_MTRR_H */