rockchip: Rename the CRU_MODE_CON fields

These should match the datasheet naming. Adjust them.

Signed-off-by: Simon Glass <sjg@chromium.org>

1 files changed, 29 insertions, 29 deletions

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
index 7ebcc405e7..b0dea7060a 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -131,35 +131,35 @@ enum {
 
 /* CRU_MODE_CON */
 enum {
-	NPLL_WORK_SHIFT		= 0xe,
-	NPLL_WORK_MASK		= 3,
-	NPLL_WORK_SLOW		= 0,
-	NPLL_WORK_NORMAL,
-	NPLL_WORK_DEEP,
-
-	GPLL_WORK_SHIFT		= 0xc,
-	GPLL_WORK_MASK		= 3,
-	GPLL_WORK_SLOW		= 0,
-	GPLL_WORK_NORMAL,
-	GPLL_WORK_DEEP,
-
-	CPLL_WORK_SHIFT		= 8,
-	CPLL_WORK_MASK		= 3,
-	CPLL_WORK_SLOW		= 0,
-	CPLL_WORK_NORMAL,
-	CPLL_WORK_DEEP,
-
-	DPLL_WORK_SHIFT		= 4,
-	DPLL_WORK_MASK		= 3,
-	DPLL_WORK_SLOW		= 0,
-	DPLL_WORK_NORMAL,
-	DPLL_WORK_DEEP,
-
-	APLL_WORK_SHIFT		= 0,
-	APLL_WORK_MASK		= 3,
-	APLL_WORK_SLOW		= 0,
-	APLL_WORK_NORMAL,
-	APLL_WORK_DEEP,
+	NPLL_MODE_SHIFT		= 0xe,
+	NPLL_MODE_MASK		= 3,
+	NPLL_MODE_SLOW		= 0,
+	NPLL_MODE_NORMAL,
+	NPLL_MODE_DEEP,
+
+	GPLL_MODE_SHIFT		= 0xc,
+	GPLL_MODE_MASK		= 3,
+	GPLL_MODE_SLOW		= 0,
+	GPLL_MODE_NORMAL,
+	GPLL_MODE_DEEP,
+
+	CPLL_MODE_SHIFT		= 8,
+	CPLL_MODE_MASK		= 3,
+	CPLL_MODE_SLOW		= 0,
+	CPLL_MODE_NORMAL,
+	CPLL_MODE_DEEP,
+
+	DPLL_MODE_SHIFT		= 4,
+	DPLL_MODE_MASK		= 3,
+	DPLL_MODE_SLOW		= 0,
+	DPLL_MODE_NORMAL,
+	DPLL_MODE_DEEP,
+
+	APLL_MODE_SHIFT		= 0,
+	APLL_MODE_MASK		= 3,
+	APLL_MODE_SLOW		= 0,
+	APLL_MODE_NORMAL,
+	APLL_MODE_DEEP,
 };
 
 /* CRU_APLL_CON0 */