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| author | Simon Glass <sjg@chromium.org> | 2015-04-29 22:26:02 -0600 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-04-30 16:13:50 -0600 |
| commit | ede9709316f6c4d18d2a3e126879af2816c0b329 (patch) | |
| tree | b50ae3f944398dd07775c14afb135362d989cc15 /arch/x86/include/asm/msr-index.h | |
| parent | bcb0c61e1a7f2a418e986044a9ade06561f8f8a8 (diff) | |
| download | blackbird-obmc-uboot-ede9709316f6c4d18d2a3e126879af2816c0b329.tar.gz blackbird-obmc-uboot-ede9709316f6c4d18d2a3e126879af2816c0b329.zip | |
x86: Add a CPU driver for baytrail
This driver supports multi-core init and sets up the CPU frequencies
correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/include/asm/msr-index.h')
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 2cbb270089..38dbb3137a 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -53,10 +53,17 @@ #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) +#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0x000000cd #define MSR_PLATFORM_INFO 0x000000ce +#define MSR_PMG_CST_CONFIG_CONTROL 0x000000e2 +#define SINGLE_PCTL (1 << 11) + #define MSR_MTRRcap 0x000000fe #define MSR_IA32_BBL_CR_CTL 0x00000119 #define MSR_IA32_BBL_CR_CTL3 0x0000011e +#define MSR_POWER_MISC 0x00000120 +#define ENABLE_ULFM_AUTOCM_MASK (1 << 2) +#define ENABLE_INDP_AUTOCM_MASK (1 << 3) #define MSR_IA32_SYSENTER_CS 0x00000174 #define MSR_IA32_SYSENTER_ESP 0x00000175 @@ -66,6 +73,7 @@ #define MSR_IA32_MCG_STATUS 0x0000017a #define MSR_IA32_MCG_CTL 0x0000017b +#define MSR_IA32_MISC_ENABLES 0x000001a0 #define MSR_OFFCORE_RSP_0 0x000001a6 #define MSR_OFFCORE_RSP_1 0x000001a7 #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad @@ -73,6 +81,7 @@ #define MSR_LBR_SELECT 0x000001c8 #define MSR_LBR_TOS 0x000001c9 +#define MSR_POWER_CTL 0x000001fc #define MSR_LBR_NHM_FROM 0x00000680 #define MSR_LBR_NHM_TO 0x000006c0 #define MSR_LBR_CORE_FROM 0x00000040 @@ -136,7 +145,7 @@ /* Run Time Average Power Limiting (RAPL) Interface */ -#define MSR_RAPL_POWER_UNIT 0x00000606 +#define MSR_PKG_POWER_SKU_UNIT 0x00000606 #define MSR_PKG_POWER_LIMIT 0x00000610 #define MSR_PKG_ENERGY_STATUS 0x00000611 @@ -158,6 +167,16 @@ #define MSR_PP1_POLICY 0x00000642 #define MSR_CORE_C1_RES 0x00000660 +#define MSR_IACORE_RATIOS 0x0000066a +#define MSR_IACORE_TURBO_RATIOS 0x0000066c +#define MSR_IACORE_VIDS 0x0000066b +#define MSR_IACORE_TURBO_VIDS 0x0000066d +#define MSR_PKG_TURBO_CFG1 0x00000670 +#define MSR_CPU_TURBO_WKLD_CFG1 0x00000671 +#define MSR_CPU_TURBO_WKLD_CFG2 0x00000672 +#define MSR_CPU_THERM_CFG1 0x00000673 +#define MSR_CPU_THERM_CFG2 0x00000674 +#define MSR_CPU_THERM_SENS_CFG 0x00000675 #define MSR_AMD64_MC0_MASK 0xc0010044 @@ -348,6 +367,7 @@ #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) #define MSR_IA32_MISC_ENABLE 0x000001a0 +#define H_MISC_DISABLE_TURBO (1 << 6) #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 |
