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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-05-25 22:35:04 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-06-04 02:39:39 -0600 |
| commit | 9c7dea602edd9027848d312e9b3b69f06c15f163 (patch) | |
| tree | 4893732c170a3a889b819482f7003491ecbac11c /arch/x86/dts/crownbay.dts | |
| parent | 2aa3a7fb1c24afd4c0e12360acccf3234d8fe019 (diff) | |
| download | blackbird-obmc-uboot-9c7dea602edd9027848d312e9b3b69f06c15f163.tar.gz blackbird-obmc-uboot-9c7dea602edd9027848d312e9b3b69f06c15f163.zip | |
x86: Refactor PIRQ routing support
PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memory-mapped IBASE) to configure the legacy
8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing
support using device tree and move it to a common place, so that we
can easily add PIRQ routing support on a new platform.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/dts/crownbay.dts')
| -rw-r--r-- | arch/x86/dts/crownbay.dts | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index fbdeade047..d68efda8df 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -6,6 +6,8 @@ /dts-v1/; +#include <dt-bindings/interrupt-router/intel-irq.h> + /include/ "skeleton.dtsi" /include/ "serial.dtsi" @@ -135,6 +137,58 @@ }; }; }; + + irq-router@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,irq-router"; + intel,pirq-config = "pci"; + intel,pirq-link = <0x60 8>; + intel,pirq-mask = <0xdee0>; + intel,pirq-routing = < + /* TunnelCreek PCI devices */ + PCI_BDF(0, 2, 0) INTA PIRQE + PCI_BDF(0, 3, 0) INTA PIRQF + PCI_BDF(0, 23, 0) INTA PIRQE + PCI_BDF(0, 24, 0) INTA PIRQF + PCI_BDF(0, 25, 0) INTA PIRQG + PCI_BDF(0, 26, 0) INTA PIRQH + PCI_BDF(0, 27, 0) INTA PIRQG + /* + * Topcliff PCI devices + * + * Note on the Crown Bay board, Topcliff chipset + * is connected to TunnelCreek PCIe port 0, so + * its bus number is 1 for its PCIe port and 2 + * for its PCI devices per U-Boot currnet PCI + * bus enumeration algorithm. + */ + PCI_BDF(1, 0, 0) INTA PIRQA + PCI_BDF(2, 0, 1) INTA PIRQA + PCI_BDF(2, 0, 2) INTA PIRQA + PCI_BDF(2, 2, 0) INTB PIRQB + PCI_BDF(2, 2, 1) INTB PIRQB + PCI_BDF(2, 2, 2) INTB PIRQB + PCI_BDF(2, 2, 3) INTB PIRQB + PCI_BDF(2, 2, 4) INTB PIRQB + PCI_BDF(2, 4, 0) INTC PIRQC + PCI_BDF(2, 4, 1) INTC PIRQC + PCI_BDF(2, 6, 0) INTD PIRQD + PCI_BDF(2, 8, 0) INTA PIRQA + PCI_BDF(2, 8, 1) INTA PIRQA + PCI_BDF(2, 8, 2) INTA PIRQA + PCI_BDF(2, 8, 3) INTA PIRQA + PCI_BDF(2, 10, 0) INTB PIRQB + PCI_BDF(2, 10, 1) INTB PIRQB + PCI_BDF(2, 10, 2) INTB PIRQB + PCI_BDF(2, 10, 3) INTB PIRQB + PCI_BDF(2, 10, 4) INTB PIRQB + PCI_BDF(2, 12, 0) INTC PIRQC + PCI_BDF(2, 12, 1) INTC PIRQC + PCI_BDF(2, 12, 2) INTC PIRQC + PCI_BDF(2, 12, 3) INTC PIRQC + PCI_BDF(2, 12, 4) INTC PIRQC + >; + }; }; }; |
