x86: ivybridge: Sort out the calls to bridge_silicon_revision()

This function is called all over the place. Convert it use the driver model
PCI API, and rationalise the calls.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

2 files changed, 39 insertions, 41 deletions

diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
index b94536c7a6..f9b03f2ef6 100644
--- a/arch/x86/cpu/ivybridge/gma.c
+++ b/arch/x86/cpu/ivybridge/gma.c
@@ -353,14 +353,13 @@ static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value)
 	return 0;
 }
 
-static int gma_pm_init_pre_vbios(void *gtt_bar)
+static int gma_pm_init_pre_vbios(void *gtt_bar, int rev)
 {
 	u32 reg32;
 
-	debug("GT Power Management Init, silicon = %#x\n",
-	      bridge_silicon_revision());
+	debug("GT Power Management Init, silicon = %#x\n", rev);
 
-	if (bridge_silicon_revision() < IVB_STEP_C0) {
+	if (rev < IVB_STEP_C0) {
 		/* 1: Enable force wake */
 		gtt_write(gtt_bar, 0xa18c, 0x00000001);
 		gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0));
@@ -370,14 +369,14 @@ static int gma_pm_init_pre_vbios(void *gtt_bar)
 		gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0));
 	}
 
-	if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+	if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
 		/* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
 		reg32 = gtt_read(gtt_bar, 0x42004);
 		reg32 |= (1 << 14) | (1 << 15);
 		gtt_write(gtt_bar, 0x42004, reg32);
 	}
 
-	if (bridge_silicon_revision() >= IVB_STEP_A0) {
+	if (rev >= IVB_STEP_A0) {
 		/* Display Reset Acknowledge Settings */
 		reg32 = gtt_read(gtt_bar, 0x45010);
 		reg32 |= (1 << 1) | (1 << 0);
@@ -386,7 +385,7 @@ static int gma_pm_init_pre_vbios(void *gtt_bar)
 
 	/* 2: Get GT SKU from GTT+0x911c[13] */
 	reg32 = gtt_read(gtt_bar, 0x911c);
-	if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+	if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
 		if (reg32 & (1 << 13)) {
 			debug("SNB GT1 Power Meter Weights\n");
 			gtt_write_powermeter(gtt_bar, snb_pm_gt1);
@@ -435,13 +434,13 @@ static int gma_pm_init_pre_vbios(void *gtt_bar)
 	reg32 = gtt_read(gtt_bar, 0xa180);
 	reg32 |= (1 << 26) | (1 << 31);
 	/* (bit 20=1 for SNB step D1+ / IVB A0+) */
-	if (bridge_silicon_revision() >= SNB_STEP_D1)
+	if (rev >= SNB_STEP_D1)
 		reg32 |= (1 << 20);
 	gtt_write(gtt_bar, 0xa180, reg32);
 
 	/* 6a: for SnB step D2+ only */
-	if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) &&
-	    (bridge_silicon_revision() >= SNB_STEP_D2)) {
+	if (((rev & BASE_REV_MASK) == BASE_REV_SNB) &&
+	    (rev >= SNB_STEP_D2)) {
 		reg32 = gtt_read(gtt_bar, 0x9400);
 		reg32 |= (1 << 7);
 		gtt_write(gtt_bar, 0x9400, reg32);
@@ -453,7 +452,7 @@ static int gma_pm_init_pre_vbios(void *gtt_bar)
 		gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1));
 	}
 
-	if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+	if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
 		reg32 = gtt_read(gtt_bar, 0x907c);
 		reg32 |= (1 << 16);
 		gtt_write(gtt_bar, 0x907c, reg32);
@@ -505,7 +504,7 @@ static int gma_pm_init_pre_vbios(void *gtt_bar)
 	gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */
 
 	/* 11a: Enable Render Standby (RC6) */
-	if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+	if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
 		/*
 		 * IvyBridge should also support DeepRenderStandby.
 		 *
@@ -539,14 +538,14 @@ static int gma_pm_init_pre_vbios(void *gtt_bar)
 	return 0;
 }
 
-int gma_pm_init_post_vbios(void *gtt_bar, const void *blob, int node)
+int gma_pm_init_post_vbios(int rev, void *gtt_bar, const void *blob, int node)
 {
 	u32 reg32, cycle_delay;
 
 	debug("GT Power Management Init (post VBIOS)\n");
 
 	/* 15: Deassert Force Wake */
-	if (bridge_silicon_revision() < IVB_STEP_C0) {
+	if (rev < IVB_STEP_C0) {
 		gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1);
 		gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0));
 	} else {
@@ -805,6 +804,7 @@ int gma_func0_init(struct udevice *dev, const void *blob, int node)
 	ulong base;
 	u32 reg32;
 	int ret;
+	int rev;
 
 	/* Enable PCH Display Port */
 	writew(0x0010, RCB_REG(DISPBDF));
@@ -813,6 +813,7 @@ int gma_func0_init(struct udevice *dev, const void *blob, int node)
 	ret = uclass_first_device(UCLASS_NORTHBRIDGE, &nbridge);
 	if (!nbridge)
 		return -ENODEV;
+	rev = bridge_silicon_revision(nbridge);
 	sandybridge_setup_graphics(nbridge, dev);
 
 	/* IGD needs to be Bus Master */
@@ -827,7 +828,7 @@ int gma_func0_init(struct udevice *dev, const void *blob, int node)
 
 	gtt_bar = (void *)dm_pci_read_bar32(dev, 0);
 	debug("GT bar %p\n", gtt_bar);
-	ret = gma_pm_init_pre_vbios(gtt_bar);
+	ret = gma_pm_init_pre_vbios(gtt_bar, rev);
 	if (ret)
 		return ret;
 
@@ -838,7 +839,7 @@ int gma_func0_init(struct udevice *dev, const void *blob, int node)
 	debug("BIOS ran in %lums\n", get_timer(start));
 #endif
 	/* Post VBIOS init */
-	ret = gma_pm_init_post_vbios(gtt_bar, blob, node);
+	ret = gma_pm_init_post_vbios(rev, gtt_bar, blob, node);
 	if (ret)
 		return ret;
 
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c
index d52eb39392..a066607a18 100644
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -19,23 +19,17 @@
 #include <asm/arch/model_206ax.h>
 #include <asm/arch/sandybridge.h>
 
-static int bridge_revision_id = -1;
-
-int bridge_silicon_revision(void)
+int bridge_silicon_revision(struct udevice *dev)
 {
-	if (bridge_revision_id < 0) {
-		struct cpuid_result result;
-		uint8_t stepping, bridge_id;
-		pci_dev_t dev;
-
-		result = cpuid(1);
-		stepping = result.eax & 0xf;
-		dev = PCI_BDF(0, 0, 0);
-		bridge_id = x86_pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0;
-		bridge_revision_id = bridge_id | stepping;
-	}
-
-	return bridge_revision_id;
+	struct cpuid_result result;
+	u16 bridge_id;
+	u8 stepping;
+
+	result = cpuid(1);
+	stepping = result.eax & 0xf;
+	dm_pci_read_config16(dev, PCI_DEVICE_ID, &bridge_id);
+	bridge_id &= 0xf0;
+	return bridge_id | stepping;
 }
 
 /*
@@ -91,45 +85,45 @@ static void add_fixed_resources(struct udevice *dev, int index)
 	}
 }
 
-static void northbridge_dmi_init(struct udevice *dev)
+static void northbridge_dmi_init(struct udevice *dev, int rev)
 {
 	/* Clear error status bits */
 	writel(0xffffffff, DMIBAR_REG(0x1c4));
 	writel(0xffffffff, DMIBAR_REG(0x1d0));
 
 	/* Steps prior to DMI ASPM */
-	if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+	if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
 		clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20),
 				1 << 21);
 	}
 
 	setbits_le32(DMIBAR_REG(0x238), 1 << 29);
 
-	if (bridge_silicon_revision() >= SNB_STEP_D0) {
+	if (rev >= SNB_STEP_D0) {
 		setbits_le32(DMIBAR_REG(0x1f8), 1 << 16);
-	} else if (bridge_silicon_revision() >= SNB_STEP_D1) {
+	} else if (rev >= SNB_STEP_D1) {
 		clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16);
 		setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23));
 	}
 
 	/* Enable ASPM on SNB link, should happen before PCH link */
-	if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB)
+	if ((rev & BASE_REV_MASK) == BASE_REV_SNB)
 		setbits_le32(DMIBAR_REG(0xd04), 1 << 4);
 
 	setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0));
 }
 
-static void northbridge_init(struct udevice *dev)
+static void northbridge_init(struct udevice *dev, int rev)
 {
 	u32 bridge_type;
 
 	add_fixed_resources(dev, 6);
-	northbridge_dmi_init(dev);
+	northbridge_dmi_init(dev, rev);
 
 	bridge_type = readl(MCHBAR_REG(0x5f10));
 	bridge_type &= ~0xff;
 
-	if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+	if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
 		/* Enable Power Aware Interrupt Routing - fixed priority */
 		clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4);
 
@@ -220,10 +214,13 @@ static int bd82x6x_northbridge_early_init(struct udevice *dev)
 
 static int bd82x6x_northbridge_probe(struct udevice *dev)
 {
+	int rev;
+
 	if (!(gd->flags & GD_FLG_RELOC))
 		return bd82x6x_northbridge_early_init(dev);
 
-	northbridge_init(dev);
+	rev = bridge_silicon_revision(dev);
+	northbridge_init(dev, rev);
 
 	return 0;
 }