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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-05-07 21:34:08 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-06-04 02:39:38 -0600 |
| commit | a65b25d148fb0a9ef7dd5fba4ae2709f5bcae0c6 (patch) | |
| tree | ddbf28ac4f0a34f5c8b62b80f59a0a93db645a01 /arch/x86/cpu/qemu/pci.c | |
| parent | 238fe16c40f640e5b78828b21990a0565f408813 (diff) | |
| download | blackbird-obmc-uboot-a65b25d148fb0a9ef7dd5fba4ae2709f5bcae0c6.tar.gz blackbird-obmc-uboot-a65b25d148fb0a9ef7dd5fba4ae2709f5bcae0c6.zip | |
x86: Support QEMU x86 targets
This commit introduces the initial U-Boot support for QEMU x86 targets.
U-Boot can boot from coreboot as a payload, or directly without coreboot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Merged in patch 'x86: qemu: Add CMD_NET to qemu-x86_defconfig
https://patchwork.ozlabs.org/patch/479745/
Diffstat (limited to 'arch/x86/cpu/qemu/pci.c')
| -rw-r--r-- | arch/x86/cpu/qemu/pci.c | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c new file mode 100644 index 0000000000..d50ab752d3 --- /dev/null +++ b/arch/x86/cpu/qemu/pci.c @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <pci.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_pci_setup_hose(struct pci_controller *hose) +{ + hose->first_busno = 0; + hose->last_busno = 0; + + /* PCI memory space */ + pci_set_region(hose->regions + 0, + CONFIG_PCI_MEM_BUS, + CONFIG_PCI_MEM_PHYS, + CONFIG_PCI_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 1, + CONFIG_PCI_IO_BUS, + CONFIG_PCI_IO_PHYS, + CONFIG_PCI_IO_SIZE, + PCI_REGION_IO); + + pci_set_region(hose->regions + 2, + CONFIG_PCI_PREF_BUS, + CONFIG_PCI_PREF_PHYS, + CONFIG_PCI_PREF_SIZE, + PCI_REGION_PREFETCH); + + pci_set_region(hose->regions + 3, + 0, + 0, + gd->ram_size, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + hose->region_count = 4; +} + +int board_pci_post_scan(struct pci_controller *hose) +{ + return 0; +} |
