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| author | Simon Glass <sjg@chromium.org> | 2014-11-12 22:42:13 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2014-11-21 07:34:12 +0100 |
| commit | 6e5b12b6144acd83dcfb4a79ea0beff787f3f545 (patch) | |
| tree | 2cbf6620bcd926e3de2d4cc0531efc05ee47723e /arch/x86/cpu/ivybridge/pci.c | |
| parent | 7430f1086429fa93e80c3951baac90e1c578898a (diff) | |
| download | blackbird-obmc-uboot-6e5b12b6144acd83dcfb4a79ea0beff787f3f545.tar.gz blackbird-obmc-uboot-6e5b12b6144acd83dcfb4a79ea0beff787f3f545.zip | |
x86: ivybridge: Enable PCI in early init
Enable PCI so we can access devices that need to be set up before relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/ivybridge/pci.c')
| -rw-r--r-- | arch/x86/cpu/ivybridge/pci.c | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c new file mode 100644 index 0000000000..c1ae658d3f --- /dev/null +++ b/arch/x86/cpu/ivybridge/pci.c @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008,2009 + * Graeme Russ, <graeme.russ@gmail.com> + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <pci.h> +#include <asm/pci.h> + +static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *table) +{ + u8 secondary; + + hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary); + if (secondary != 0) + pci_hose_scan_bus(hose, secondary); +} + +static struct pci_config_table pci_ivybridge_config_table[] = { + /* vendor, device, class, bus, dev, func */ + { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge }, + {} +}; + +void board_pci_setup_hose(struct pci_controller *hose) +{ + hose->config_table = pci_ivybridge_config_table; + hose->first_busno = 0; + hose->last_busno = 0; + + /* PCI memory space */ + pci_set_region(hose->regions + 0, + CONFIG_PCI_MEM_BUS, + CONFIG_PCI_MEM_PHYS, + CONFIG_PCI_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 1, + CONFIG_PCI_IO_BUS, + CONFIG_PCI_IO_PHYS, + CONFIG_PCI_IO_SIZE, + PCI_REGION_IO); + + pci_set_region(hose->regions + 2, + CONFIG_PCI_PREF_BUS, + CONFIG_PCI_PREF_PHYS, + CONFIG_PCI_PREF_SIZE, + PCI_REGION_PREFETCH); + + hose->region_count = 3; +} |
