powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto'

If property 'fsl,sec-era' is already present, it is updated.
This property is required so that applications can ascertain which
descriptor commands are supported on a particular CAAM version.

Signed-off-by: Vakul Garg <vakul@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

3 files changed, 92 insertions, 1 deletions

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 16d7f6a222..3a268aa0a0 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -607,6 +607,14 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	/* delete crypto node if not on an E-processor */
 	if (!IS_E_PROCESSOR(get_svr()))
 		fdt_fixup_crypto_node(blob, 0);
+#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
+	else {
+		ccsr_sec_t __iomem *sec;
+
+		sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+		fdt_fixup_crypto_node(blob, in_be32(&sec->secvid_ms));
+	}
+#endif
 
 	fdt_fixup_ethernet(blob);
 
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 1986fea030..284709428d 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -297,10 +297,86 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev)
 		       fdt_strerror(err));
 }
 #elif CONFIG_SYS_FSL_SEC_COMPAT >= 4  /* SEC4 */
+static u8 caam_get_era(void)
+{
+	static const struct {
+		u16 ip_id;
+		u8 maj_rev;
+		u8 era;
+	} caam_eras[] = {
+		{0x0A10, 1, 1},
+		{0x0A10, 2, 2},
+		{0x0A12, 1, 3},
+		{0x0A14, 1, 3},
+		{0x0A14, 2, 4},
+		{0x0A16, 1, 4},
+		{0x0A10, 3, 4},
+		{0x0A11, 1, 4},
+		{0x0A18, 1, 4},
+		{0x0A11, 2, 5},
+		{0x0A12, 2, 5},
+		{0x0A13, 1, 5},
+		{0x0A1C, 1, 5}
+	};
+
+	ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+	u32 secvid_ms = in_be32(&sec->secvid_ms);
+	u32 ccbvid = in_be32(&sec->ccbvid);
+	u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >>
+				SEC_SECVID_MS_IPID_SHIFT;
+	u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >>
+				SEC_SECVID_MS_MAJ_REV_SHIFT;
+	u8 era = (ccbvid & SEC_CCBVID_ERA_MASK) >> SEC_CCBVID_ERA_SHIFT;
+
+	int i;
+
+	if (era)	/* This is '0' prior to CAAM ERA-6 */
+		return era;
+
+	for (i = 0; i < ARRAY_SIZE(caam_eras); i++)
+		if (caam_eras[i].ip_id == ip_id &&
+		    caam_eras[i].maj_rev == maj_rev)
+			return caam_eras[i].era;
+
+	return 0;
+}
+
+static void fdt_fixup_crypto_era(void *blob, u32 era)
+{
+	int err;
+	int crypto_node;
+
+	crypto_node = fdt_path_offset(blob, "crypto");
+	if (crypto_node < 0) {
+		printf("WARNING: Missing crypto node\n");
+		return;
+	}
+
+	err = fdt_setprop(blob, crypto_node, "fsl,sec-era", &era,
+			  sizeof(era));
+	if (err < 0) {
+		printf("ERROR: could not set fsl,sec-era property: %s\n",
+		       fdt_strerror(err));
+	}
+}
+
 void fdt_fixup_crypto_node(void *blob, int sec_rev)
 {
-	if (!sec_rev)
+	u8 era;
+
+	if (!sec_rev) {
 		fdt_del_node_and_alias(blob, "crypto");
+		return;
+	}
+
+	/* Add SEC ERA information in compatible */
+	era = caam_get_era();
+	if (era) {
+		fdt_fixup_crypto_era(blob, era);
+	} else {
+		printf("WARNING: Unable to get ERA for CAAM rev: %d\n",
+			sec_rev);
+	}
 }
 #endif
 
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 67b1a44ab8..4eb3f79230 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2748,6 +2748,12 @@ typedef struct ccsr_sec {
 #define SEC_CHANUM_MS_JRNUM_SHIFT	28
 #define SEC_CHANUM_MS_DECONUM_MASK	0x0f000000
 #define SEC_CHANUM_MS_DECONUM_SHIFT	24
+#define SEC_SECVID_MS_IPID_MASK	0xffff0000
+#define SEC_SECVID_MS_IPID_SHIFT	16
+#define SEC_SECVID_MS_MAJ_REV_MASK	0x0000ff00
+#define SEC_SECVID_MS_MAJ_REV_SHIFT	8
+#define SEC_CCBVID_ERA_MASK		0xff000000
+#define SEC_CCBVID_ERA_SHIFT		24
 #endif
 
 typedef struct ccsr_qman {
@@ -2983,6 +2989,7 @@ struct ccsr_pman {
 #endif
 #define CONFIG_SYS_MDIO1_OFFSET			0x24000
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
+#define CONFIG_SYS_FSL_SEC_OFFSET		0x30000
 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET	0xE3100
 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
 #define CONFIG_SYS_SNVS_OFFSET			0xE6000