diff options
| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2011-02-01 15:55:58 +0000 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-03-29 07:41:37 -0500 |
| commit | b03a466d6ceb9dbfd1a1638f355e9c8b4833259f (patch) | |
| tree | 5969f3c69be00b44b0fdf7c00c1d180d414e4b09 /arch/powerpc/include | |
| parent | 2d7534a344412409d03e4a341614e4320c48879b (diff) | |
| download | blackbird-obmc-uboot-b03a466d6ceb9dbfd1a1638f355e9c8b4833259f.tar.gz blackbird-obmc-uboot-b03a466d6ceb9dbfd1a1638f355e9c8b4833259f.zip | |
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs
The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe. Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 22086a0f0e..6c16681b7f 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -90,12 +90,14 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 #elif defined(CONFIG_P1012) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 #elif defined(CONFIG_P1013) @@ -117,12 +119,14 @@ #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 #elif defined(CONFIG_P1021) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 #elif defined(CONFIG_P1022) |
