Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E
  powerpc/mpc85xx: Workaround for erratum CPU_A011
  powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
  powerpc/P4080: Check SVR for CPU22 workaround
  lib/powerpc: addrmap_phys_to_virt() should return a pointer
  powerpc/85xx: clean up P1022DS board configuration header file
  powerpc/85xx: fdt_set_phy_handle() should return an error code
  powerpc/85xx: minor clean-ups to the P2020DS board header file
  powerpc/p1010rdb: add readme document for p1010rdb
  powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting
  powerpc/mpc85xx:Add debugger support for e500v2 SoC
  powerpc/85xx:Fix NAND code base to support debugger
  powerpc/85xx:Make debug exception vector accessible
  powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger
  PATCH 1/4][v4] doc:Add documentation for e500 external debugger support
  powerpc/p1010rdb: update mux config of p1010rdb board
  powerpc/mpc85xx:Add BSC9131 RDB Support
  powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
  powerpc/85xx: Add USB device-tree fixup for various platforms

Signed-off-by: Wolfgang Denk <wd@denx.de>

10 files changed, 180 insertions, 110 deletions

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index c512b337f1..7d65aa7363 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -70,6 +70,7 @@ COBJS-$(CONFIG_PPC_P3041)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P3060)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P4080)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P5020)	+= ddr-gen3.o
+COBJS-$(CONFIG_BSC9131)		+= ddr-gen3.o
 
 COBJS-$(CONFIG_CPM2)	+= ether_fcc.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 2ed5a98424..4e1a54ad0c 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -33,9 +33,7 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if (IS_SVR_REV(svr, 1, 0)) {
 		switch (SVR_SOC_VER(svr)) {
 		case SVR_P1013:
-		case SVR_P1013_E:
 		case SVR_P1022:
-		case SVR_P1022_E:
 			puts("Work-around for Erratum SATA A001 enabled\n");
 		}
 	}
@@ -51,7 +49,16 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	puts("Work-around for Erratum SERDES-A005 enabled\n");
 #endif
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
-	puts("Work-around for Erratum CPU22 enabled\n");
+	if (SVR_MAJ(svr) < 3)
+		puts("Work-around for Erratum CPU22 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
+	/*
+	 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+	 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
+	 */
+	if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3)
+		puts("Work-around for Erratum CPU-A011 enabled\n");
 #endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
 	puts("Work-around for Erratum CPU-A003999 enabled\n");
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 2cd5db7c59..fc6c2877d2 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -308,10 +308,18 @@ int cpu_init_r(void)
 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 #endif
 
-#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
-	flush_dcache();
-	mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
-	sync();
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
+	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
+	/*
+	 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+	 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+	 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
+	 */
+	if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) {
+		flush_dcache();
+		mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
+		sync();
+	}
 #endif
 
 	puts ("L2:    ");
@@ -354,8 +362,7 @@ int cpu_init_r(void)
 		break;
 	case 0x1:
 		if (ver == SVR_8540 || ver == SVR_8560   ||
-		    ver == SVR_8541 || ver == SVR_8541_E ||
-		    ver == SVR_8555 || ver == SVR_8555_E) {
+		    ver == SVR_8541 || ver == SVR_8555) {
 			puts("128 KB ");
 			/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
 			cache_ctl = 0xc4000000;
@@ -366,8 +373,7 @@ int cpu_init_r(void)
 		break;
 	case 0x2:
 		if (ver == SVR_8540 || ver == SVR_8560   ||
-		    ver == SVR_8541 || ver == SVR_8541_E ||
-		    ver == SVR_8555 || ver == SVR_8555_E) {
+		    ver == SVR_8541 || ver == SVR_8555) {
 			puts("256 KB ");
 			/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
 			cache_ctl = 0xc8000000;
@@ -403,8 +409,7 @@ int cpu_init_r(void)
 		puts("enabled\n");
 	}
 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
-	if ((SVR_SOC_VER(svr) == SVR_P2040) ||
-	    (SVR_SOC_VER(svr) == SVR_P2040_E)) {
+	if (SVR_SOC_VER(svr) == SVR_P2040) {
 		puts("N/A\n");
 		goto skip_l2;
 	}
@@ -506,9 +511,7 @@ skip_l2:
 	 */
 	if (IS_SVR_REV(svr, 1, 0) &&
 	    ((SVR_SOC_VER(svr) == SVR_P1022) ||
-	     (SVR_SOC_VER(svr) == SVR_P1022_E) ||
-	     (SVR_SOC_VER(svr) == SVR_P1013) ||
-	     (SVR_SOC_VER(svr) == SVR_P1013_E))) {
+	     (SVR_SOC_VER(svr) == SVR_P1013))) {
 		fsl_sata_reg_t *reg;
 
 		/* first SATA controller */
@@ -537,7 +540,7 @@ void arch_preboot_os(void)
 	 * disabled by the time we get called.
 	 */
 	msr = mfmsr();
-	msr &= ~(MSR_ME|MSR_CE|MSR_DE);
+	msr &= ~(MSR_ME|MSR_CE);
 	mtmsr(msr);
 
 	setup_ivors();
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 091af7c95a..dacfdd15ea 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009-2011 Freescale Semiconductor, Inc
+ * Copyright 2009-2012 Freescale Semiconductor, Inc
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -53,6 +53,36 @@ void setup_ifc(void)
 
 	asm volatile("isync;msync;tlbwe;isync");
 
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
+/*
+ * TLB entry for debuggging in AS1
+ * Create temporary TLB entry in AS0 to handle debug exception
+ * As on debug exception MSR is cleared i.e. Address space is changed
+ * to 0. A TLB entry (in AS0) is required to handle debug exception generated
+ * in AS1.
+ *
+ * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
+ * bacause flash's physical address is going to change as
+ * CONFIG_SYS_FLASH_BASE_PHYS.
+ */
+	_mas0 = MAS0_TLBSEL(1) |
+			MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB);
+	_mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT |
+			MAS1_TSIZE(BOOKE_PAGESZ_4M);
+	_mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
+	_mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
+	_mas7 = FSL_BOOKE_MAS7(flash_phys);
+
+	mtspr(MAS0, _mas0);
+	mtspr(MAS1, _mas1);
+	mtspr(MAS2, _mas2);
+	mtspr(MAS3, _mas3);
+	mtspr(MAS7, _mas7);
+
+	asm volatile("isync;msync;tlbwe;isync");
+#endif
+
+	/* Change flash's physical address */
 	out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
 	out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
 	out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
index f33db021f1..bf7a6f6be6 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
@@ -26,32 +26,6 @@
 
 void cpu_init_f(void)
 {
-#ifdef CONFIG_FSL_LBC
-	fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
-	/*
-	 * LCRR - Clock Ratio Register - set up local bus timing
-	 * when needed
-	 */
-	out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
-
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
-	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
-	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
-#else
-#error  CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM must be defined
-#endif
-#endif
-#ifdef CONFIG_FSL_IFC
-#ifndef	CONFIG_SYS_FSL_ERRATUM_IFC_A003399
-#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
-	set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
-	set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
-	set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
-#endif
-#endif
-#endif
-
 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
 	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 977770e99d..21c3ad49bf 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -139,16 +139,14 @@ static inline u32 l2cache_size(void)
 		break;
 	case 0x1:
 		if (ver == SVR_8540 || ver == SVR_8560   ||
-		    ver == SVR_8541 || ver == SVR_8541_E ||
-		    ver == SVR_8555 || ver == SVR_8555_E)
+		    ver == SVR_8541 || ver == SVR_8555)
 			return 128;
 		else
 			return 256;
 		break;
 	case 0x2:
 		if (ver == SVR_8540 || ver == SVR_8560   ||
-		    ver == SVR_8541 || ver == SVR_8541_E ||
-		    ver == SVR_8555 || ver == SVR_8555_E)
+		    ver == SVR_8541 || ver == SVR_8555)
 			return 256;
 		else
 			return 512;
@@ -231,8 +229,7 @@ static inline void ft_fixup_l2cache(void *blob)
 	int has_l2 = 1;
 
 	/* P2040/P2040E has no L2, so dont set any L2 props */
-	if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
-	    (SVR_SOC_VER(get_svr()) == SVR_P2040_E))
+	if (SVR_SOC_VER(get_svr()) == SVR_P2040)
 		has_l2 = 0;
 
 	size = (l2cfg0 & 0x3fff) * 64 * 1024;
@@ -407,7 +404,7 @@ static void ft_fixup_qe_snum(void *blob)
 	unsigned int svr;
 
 	svr = mfspr(SPRN_SVR);
-	if (SVR_SOC_VER(svr) == SVR_8569_E) {
+	if (SVR_SOC_VER(svr) == SVR_8569) {
 		if(IS_SVR_REV(svr, 1, 0))
 			do_fixup_by_compat_u32(blob, "fsl,qe",
 				"fsl,qe-num-snums", 46, 1);
diff --git a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c
index f68f28191f..eec4ffe516 100644
--- a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c
@@ -78,7 +78,7 @@ enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
 	prtcl = serdes_cfg_tbl[cfg][lane];
 
 	/* P2040[e] does not support XAUI */
-	if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1))
+	if (ver == SVR_P2040 && prtcl == XAUI_FM1)
 		prtcl = NONE;
 
 	return prtcl;
@@ -94,7 +94,7 @@ int is_serdes_prtcl_valid(u32 prtcl)
 		return 0;
 
 	/* P2040[e] does not support XAUI */
-	if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1))
+	if (ver == SVR_P2040 && prtcl == XAUI_FM1)
 		return 0;
 
 	for (i = 0; i < SRDS_MAX_LANES; i++) {
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index c81e19c0e9..1860684c11 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -143,23 +143,40 @@ __secondary_start_page:
 	mtspr	L1CSR2,r8
 #endif
 
-#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
-	mfspr	r8,L1CSR2
-	oris	r8,r8,(L1CSR2_DCWS)@h
-	mtspr	L1CSR2,r8
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
+	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
+	/*
+	 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+	 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+	 * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
+	 */
+	mfspr   r3,SPRN_SVR
+	rlwinm	r6,r3,24,~0x800		/* clear E bit */
+
+	lis	r5,SVR_P4080@h
+	ori	r5,r5,SVR_P4080@l
+	cmpw	r6,r5
+	bne	1f
+
+	rlwinm  r3,r3,0,0xf0
+	li      r5,0x30
+	cmpw    r3,r5
+	bge     2f
+1:
+	mfspr	r3,L1CSR2
+	oris	r3,r3,(L1CSR2_DCWS)@h
+	mtspr	L1CSR2,r3
+2:
 #endif
 
 #ifdef CONFIG_BACKSIDE_L2_CACHE
 	/* skip L2 setup on P2040/P2040E as they have no L2 */
-	mfspr	r2,SPRN_SVR
+	mfspr	r3,SPRN_SVR
+	rlwinm	r6,r3,24,~0x800		/* clear E bit of SVR */
+
 	lis	r3,SVR_P2040@h
 	ori	r3,r3,SVR_P2040@l
-	cmpw	r2,r3
-	beq 3f
-
-	lis	r3,SVR_P2040_E@h
-	ori	r3,r3,SVR_P2040_E@l
-	cmpw	r2,r3
+	cmpw	r6,r3
 	beq 3f
 
 	/* Enable/invalidate the L2 cache */
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 8e99ef6c68..6aabc30c28 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -82,6 +82,9 @@
 	.globl _start_e500
 
 _start_e500:
+/* Enable debug exception */
+	li	r1,MSR_DE
+	mtmsr 	r1
 
 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
 	/* ISBC uses L2 as stack.
@@ -179,6 +182,72 @@ l2_disabled:
 	andi.	r1,r3,L1CSR0_DCE@l
 	beq	2b
 
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
+/*
+ * TLB entry for debuggging in AS1
+ * Create temporary TLB entry in AS0 to handle debug exception
+ * As on debug exception MSR is cleared i.e. Address space is changed
+ * to 0. A TLB entry (in AS0) is required to handle debug exception generated
+ * in AS1.
+ */
+
+	lis     r6,FSL_BOOKE_MAS0(1,
+			CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@h
+	ori     r6,r6,FSL_BOOKE_MAS0(1,
+			CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@l
+
+#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
+/*
+ * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
+ * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
+ * and this window is outside of 4K boot window.
+ */
+	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@h
+	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@l
+
+	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000,
+							(MAS2_I|MAS2_G))@h
+	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000,
+							(MAS2_I|MAS2_G))@l
+
+	/* The 85xx has the default boot window 0xff800000 - 0xffffffff */
+	lis     r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
+	ori     r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
+	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
+	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
+
+	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@h
+	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@l
+
+	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
+						(MAS3_SX|MAS3_SW|MAS3_SR))@h
+	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
+						(MAS3_SX|MAS3_SW|MAS3_SR))@l
+#else
+/*
+ * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
+ * because "nexti" will resize TLB to 4K
+ */
+	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h
+	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l
+
+	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I))@h
+	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,
+							(MAS2_I))@l
+	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
+						(MAS3_SX|MAS3_SW|MAS3_SR))@h
+	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
+						(MAS3_SX|MAS3_SW|MAS3_SR))@l
+#endif
+	mtspr   MAS0,r6
+	mtspr   MAS1,r7
+	mtspr   MAS2,r8
+	mtspr   MAS3,r9
+	tlbwe
+	isync
+#endif
+
 /*
  * Ne need to setup interrupt vector for NAND SPL
  * because NAND SPL never compiles it.
@@ -733,8 +802,8 @@ create_init_ram_area:
 	msync
 	tlbwe
 
-	lis	r6,MSR_IS|MSR_DS@h
-	ori	r6,r6,MSR_IS|MSR_DS@l
+	lis	r6,MSR_IS|MSR_DS|MSR_DE@h
+	ori	r6,r6,MSR_IS|MSR_DS|MSR_DE@l
 	lis	r7,switch_as@h
 	ori	r7,r7,switch_as@l
 
@@ -1372,17 +1441,24 @@ relocate_code:
 7:	sync			/* Wait for all icbi to complete on bus */
 	isync
 
-	/*
-	 * Re-point the IVPR at RAM
-	 */
-	mtspr	IVPR,r10
-
 /*
  * We are done. Do not return, instead branch to second part of board
  * initialization, now running from RAM.
  */
 
 	addi	r0,r10,in_ram - _start + _START_OFFSET
+
+	/*
+	 * As IVPR is going to point RAM address,
+	 * Make sure IVOR15 has valid opcode to support debugger
+	 */
+	mtspr	IVOR15,r0
+
+	/*
+	 * Re-point the IVPR at RAM
+	 */
+	mtspr	IVPR,r10
+
 	mtlr	r0
 	blr				/* NEVER RETURNS! */
 	.globl	in_ram
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 0365ca8aa2..cbc674211a 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ * Copyright 2009-2012 Freescale Semiconductor, Inc.
  *
  * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
  * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
@@ -37,82 +37,47 @@ DECLARE_GLOBAL_DATA_PTR;
 struct cpu_type cpu_type_list [] = {
 #if defined(CONFIG_MPC85xx)
 	CPU_TYPE_ENTRY(8533, 8533, 1),
-	CPU_TYPE_ENTRY(8533, 8533_E, 1),
 	CPU_TYPE_ENTRY(8535, 8535, 1),
-	CPU_TYPE_ENTRY(8535, 8535_E, 1),
 	CPU_TYPE_ENTRY(8536, 8536, 1),
-	CPU_TYPE_ENTRY(8536, 8536_E, 1),
 	CPU_TYPE_ENTRY(8540, 8540, 1),
 	CPU_TYPE_ENTRY(8541, 8541, 1),
-	CPU_TYPE_ENTRY(8541, 8541_E, 1),
 	CPU_TYPE_ENTRY(8543, 8543, 1),
-	CPU_TYPE_ENTRY(8543, 8543_E, 1),
 	CPU_TYPE_ENTRY(8544, 8544, 1),
-	CPU_TYPE_ENTRY(8544, 8544_E, 1),
 	CPU_TYPE_ENTRY(8545, 8545, 1),
-	CPU_TYPE_ENTRY(8545, 8545_E, 1),
-	CPU_TYPE_ENTRY(8547, 8547_E, 1),
+	CPU_TYPE_ENTRY(8547, 8547, 1),
 	CPU_TYPE_ENTRY(8548, 8548, 1),
-	CPU_TYPE_ENTRY(8548, 8548_E, 1),
 	CPU_TYPE_ENTRY(8555, 8555, 1),
-	CPU_TYPE_ENTRY(8555, 8555_E, 1),
 	CPU_TYPE_ENTRY(8560, 8560, 1),
 	CPU_TYPE_ENTRY(8567, 8567, 1),
-	CPU_TYPE_ENTRY(8567, 8567_E, 1),
 	CPU_TYPE_ENTRY(8568, 8568, 1),
-	CPU_TYPE_ENTRY(8568, 8568_E, 1),
 	CPU_TYPE_ENTRY(8569, 8569, 1),
-	CPU_TYPE_ENTRY(8569, 8569_E, 1),
 	CPU_TYPE_ENTRY(8572, 8572, 2),
-	CPU_TYPE_ENTRY(8572, 8572_E, 2),
 	CPU_TYPE_ENTRY(P1010, P1010, 1),
-	CPU_TYPE_ENTRY(P1010, P1010_E, 1),
 	CPU_TYPE_ENTRY(P1011, P1011, 1),
-	CPU_TYPE_ENTRY(P1011, P1011_E, 1),
 	CPU_TYPE_ENTRY(P1012, P1012, 1),
-	CPU_TYPE_ENTRY(P1012, P1012_E, 1),
 	CPU_TYPE_ENTRY(P1013, P1013, 1),
-	CPU_TYPE_ENTRY(P1013, P1013_E, 1),
-	CPU_TYPE_ENTRY(P1014, P1014_E, 1),
 	CPU_TYPE_ENTRY(P1014, P1014, 1),
-	CPU_TYPE_ENTRY(P1015, P1015_E, 1),
 	CPU_TYPE_ENTRY(P1015, P1015, 1),
-	CPU_TYPE_ENTRY(P1016, P1016_E, 1),
 	CPU_TYPE_ENTRY(P1016, P1016, 1),
 	CPU_TYPE_ENTRY(P1017, P1017, 1),
-	CPU_TYPE_ENTRY(P1017, P1017_E, 1),
 	CPU_TYPE_ENTRY(P1020, P1020, 2),
-	CPU_TYPE_ENTRY(P1020, P1020_E, 2),
 	CPU_TYPE_ENTRY(P1021, P1021, 2),
-	CPU_TYPE_ENTRY(P1021, P1021_E, 2),
 	CPU_TYPE_ENTRY(P1022, P1022, 2),
-	CPU_TYPE_ENTRY(P1022, P1022_E, 2),
 	CPU_TYPE_ENTRY(P1023, P1023, 2),
-	CPU_TYPE_ENTRY(P1023, P1023_E, 2),
 	CPU_TYPE_ENTRY(P1024, P1024, 2),
-	CPU_TYPE_ENTRY(P1024, P1024_E, 2),
 	CPU_TYPE_ENTRY(P1025, P1025, 2),
-	CPU_TYPE_ENTRY(P1025, P1025_E, 2),
 	CPU_TYPE_ENTRY(P2010, P2010, 1),
-	CPU_TYPE_ENTRY(P2010, P2010_E, 1),
 	CPU_TYPE_ENTRY(P2020, P2020, 2),
-	CPU_TYPE_ENTRY(P2020, P2020_E, 2),
 	CPU_TYPE_ENTRY(P2040, P2040, 4),
-	CPU_TYPE_ENTRY(P2040, P2040_E, 4),
 	CPU_TYPE_ENTRY(P2041, P2041, 4),
-	CPU_TYPE_ENTRY(P2041, P2041_E, 4),
 	CPU_TYPE_ENTRY(P3041, P3041, 4),
-	CPU_TYPE_ENTRY(P3041, P3041_E, 4),
 	CPU_TYPE_ENTRY_MASK(P3060, P3060, 6, 0xf3),
-	CPU_TYPE_ENTRY_MASK(P3060, P3060_E, 6, 0xf3),
 	CPU_TYPE_ENTRY(P4040, P4040, 4),
-	CPU_TYPE_ENTRY(P4040, P4040_E, 4),
 	CPU_TYPE_ENTRY(P4080, P4080, 8),
-	CPU_TYPE_ENTRY(P4080, P4080_E, 8),
 	CPU_TYPE_ENTRY(P5010, P5010, 1),
-	CPU_TYPE_ENTRY(P5010, P5010_E, 1),
 	CPU_TYPE_ENTRY(P5020, P5020, 2),
-	CPU_TYPE_ENTRY(P5020, P5020_E, 2),
+	CPU_TYPE_ENTRY(BSC9130, 9130, 1),
+	CPU_TYPE_ENTRY(BSC9131, 9131, 1),
 #elif defined(CONFIG_MPC86xx)
 	CPU_TYPE_ENTRY(8610, 8610, 1),
 	CPU_TYPE_ENTRY(8641, 8641, 2),