Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

7 files changed, 149 insertions, 210 deletions

diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile
index ab80dd7723..5dfd65b882 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -12,11 +12,11 @@ LIB	= $(obj)lib8xxx.o
 
 ifneq ($(CPU),mpc83xx)
 COBJS-y	+= cpu.o
-COBJS-$(CONFIG_PCI)	+= pci_cfg.o
 endif
 
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
+COBJS-$(CONFIG_SYS_SRIO) += srio.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 6d582e97d4..e3888ff6ef 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -469,8 +469,9 @@ phys_size_t fsl_ddr_sdram(void)
 	/* Check for 4G or more.  Bad. */
 	if (total_memory >= (1ull << 32)) {
 		printf("Detected %lld MB of memory\n", total_memory >> 20);
-		printf("This U-Boot only supports < 4G of DDR\n");
-		printf("You could rebuild it with CONFIG_PHYS_64BIT\n");
+		printf("       This U-Boot only supports < 4G of DDR\n");
+		printf("       You could rebuild it with CONFIG_PHYS_64BIT\n");
+		printf("       "); /* re-align to match init_func_ram print */
 		total_memory = CONFIG_MAX_MEM_MAPPED;
 	}
 #endif
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
index 774c0e4b42..c641e85068 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008, 2010 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the Free
@@ -387,3 +387,23 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo)
 				"Memory controller interleaving disabled.\n");
 	}
 }
+
+int fsl_use_spd(void)
+{
+	int use_spd = 0;
+
+#ifdef CONFIG_DDR_SPD
+	/* if hwconfig is not enabled, or "sdram" is not defined, use spd */
+	if (hwconfig_sub("fsl_ddr", "sdram")) {
+		if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "spd"))
+			use_spd = 1;
+		else if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "fixed"))
+			use_spd = 0;
+		else
+			use_spd = 1;
+	} else
+		use_spd = 1;
+#endif
+
+	return use_spd;
+}
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 54e60bb1ae..0c166fd6c9 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
  *
  * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
  * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
@@ -28,6 +28,7 @@
 #include <fdt_support.h>
 #include <asm/mp.h>
 #include <asm/fsl_enet.h>
+#include <asm/fsl_serdes.h>
 
 #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
 static int ft_del_cpuhandle(void *blob, int cpuhandle)
@@ -239,3 +240,23 @@ int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc)
 	return fdt_setprop_string(blob, offset, "phy-connection-type",
 					 fsl_phy_enet_if_str[phyc]);
 }
+
+#ifdef CONFIG_SYS_SRIO
+void ft_srio_setup(void *blob)
+{
+#ifdef CONFIG_SRIO1
+	if (!is_serdes_configured(SRIO1)) {
+		fdt_del_node_and_alias(blob, "rio0");
+	}
+#else
+	fdt_del_node_and_alias(blob, "rio0");
+#endif
+#ifdef CONFIG_SRIO2
+	if (!is_serdes_configured(SRIO2)) {
+		fdt_del_node_and_alias(blob, "rio1");
+	}
+#else
+	fdt_del_node_and_alias(blob, "rio1");
+#endif
+}
+#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
index fcef40c5b8..7598ebf457 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2010 Freescale Semiconductor, Inc.
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -9,6 +9,16 @@
 #include <common.h>
 #include <asm/fsl_lbc.h>
 
+#ifdef CONFIG_MPC85xx
+/* Boards should provide their own version of this if they use lbc sdram */
+void __lbc_sdram_init(void)
+{
+	/* Do nothing */
+}
+void lbc_sdram_init(void) __attribute__((weak, alias("__lbc_sdram_init")));
+#endif
+
+
 void print_lbc_regs(void)
 {
 	int i;
@@ -24,6 +34,11 @@ void init_early_memctl_regs(void)
 {
 	uint init_br1 = 1;
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
+	/* Set the local bus monitor timeout value to the maximum */
+	clrsetbits_be32(&(LBC_BASE_ADDR)->lbcr, LBCR_BMT|LBCR_BMTPS, 0xf);
+#endif
+
 #ifdef CONFIG_MPC85xx
 	/* if cs1 is already set via debugger, leave cs0/cs1 alone */
 	if (get_lbc_br(1) & BR_V)
diff --git a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c
deleted file mode 100644
index 53236a36f8..0000000000
--- a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <pci.h>
-
-struct pci_info {
-	u32	cfg;
-};
-
-/* The cfg field is a bit mask in which each bit represents the value of
- * cfg_IO_ports[] signal and the bit is set if the interface would be
- * enabled based on the value of cfg_IO_ports[] signal
- *
- * On MPC86xx/PQ3 based systems:
- *   we extract cfg_IO_ports from GUTS register PORDEVSR
- *
- * cfg_IO_ports only exist on systems w/PCIe (we set cfg 0 for systems
- * without PCIe)
- */
-
-#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8560)
-static struct pci_info pci_config_info[] =
-{
-	[LAW_TRGT_IF_PCI] = {
-		.cfg =   0,
-	},
-};
-#elif defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
-static struct pci_info pci_config_info[] =
-{
-	[LAW_TRGT_IF_PCI] = {
-		.cfg =   0,
-	},
-};
-#elif defined(CONFIG_MPC8536)
-static struct pci_info pci_config_info[] =
-{
-};
-#elif defined(CONFIG_MPC8544)
-static struct pci_info pci_config_info[] =
-{
-	[LAW_TRGT_IF_PCI] = {
-		.cfg =   0,
-	},
-	[LAW_TRGT_IF_PCIE_1] = {
-		.cfg =   (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) |
-			 (1 << 6) | (1 << 7),
-	},
-	[LAW_TRGT_IF_PCIE_2] = {
-		.cfg =   (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7),
-	},
-	[LAW_TRGT_IF_PCIE_3] = {
-		.cfg =   (1 << 6) | (1 << 7),
-	},
-};
-#elif defined(CONFIG_MPC8548)
-static struct pci_info pci_config_info[] =
-{
-	[LAW_TRGT_IF_PCI_1] = {
-		.cfg =   0,
-	},
-	[LAW_TRGT_IF_PCI_2] = {
-		.cfg =   0,
-	},
-	/* PCI_2 is always host and we dont use iosel to determine enable/disable */
-	[LAW_TRGT_IF_PCIE_1] = {
-		.cfg =   (1 << 3) | (1 << 4) | (1 << 7),
-	},
-};
-#elif defined(CONFIG_MPC8568)
-static struct pci_info pci_config_info[] =
-{
-	[LAW_TRGT_IF_PCI] = {
-		.cfg =   0,
-	},
-	[LAW_TRGT_IF_PCIE_1] = {
-		.cfg =   (1 << 3) | (1 << 4) | (1 << 7),
-	},
-};
-#elif defined(CONFIG_MPC8569)
-static struct pci_info pci_config_info[] =
-{
-	[LAW_TRGT_IF_PCIE_1] = {
-		.cfg =   (1 << 0) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) |
-			 (1 << 8) | (1 << 0xc) | (1 << 0xf),
-	},
-};
-#elif defined(CONFIG_MPC8572)
-static struct pci_info pci_config_info[] =
-{
-	[LAW_TRGT_IF_PCIE_1] = {
-		.cfg =   (1 << 2) | (1 << 3) | (1 << 7) |
-			 (1 << 0xb) | (1 << 0xc) | (1 << 0xf),
-	},
-	[LAW_TRGT_IF_PCIE_2] = {
-		.cfg =   (1 << 3) | (1 << 7),
-	},
-	[LAW_TRGT_IF_PCIE_3] = {
-		.cfg =   (1 << 7),
-	},
-};
-#elif defined(CONFIG_MPC8610)
-static struct pci_info pci_config_info[] =
-{
-	[LAW_TRGT_IF_PCI_1] = {
-		.cfg =   0,
-	},
-	[LAW_TRGT_IF_PCIE_1] = {
-		.cfg =   (1 << 1) | (1 << 4),
-	},
-	[LAW_TRGT_IF_PCIE_2] = {
-		.cfg =   (1 << 0) | (1 << 4),
-	},
-};
-#elif defined(CONFIG_MPC8641)
-static struct pci_info pci_config_info[] =
-{
-	[LAW_TRGT_IF_PCIE_1] = {
-		.cfg =   (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) |
-			 (1 << 7) | (1 << 0xf),
-	},
-	[LAW_TRGT_IF_PCIE_2] = {
-		.cfg =   (1 << 3) | (1 << 0xe) | (1 << 0xf),
-	},
-};
-#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
-      defined(CONFIG_P1012) || defined(CONFIG_P1021)
-static struct pci_info pci_config_info[] =
-{
-	[LAW_TRGT_IF_PCIE_1] = {
-		.cfg =   (1 << 0) | (1 << 6) | (1 << 0xe) | (1 << 0xf),
-	},
-	[LAW_TRGT_IF_PCIE_2] = {
-		.cfg =   (1 << 0xe),
-	},
-};
-#elif defined(CONFIG_P1013) || defined(CONFIG_P1022)
-static struct pci_info pci_config_info[] =
-{
-	[LAW_TRGT_IF_PCIE_1] = {
-		.cfg =   (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xa) |
-			 (1 << 0xb) | (1 << 0xd) | (1 << 0xe) |
-			 (1 << 0xf) | (1 << 0x15) | (1 << 0x16) |
-			 (1 << 0x17) | (1 << 0x18) | (1 << 0x19) |
-			 (1 << 0x1a) | (1 << 0x1b) | (1 << 0x1c) |
-			 (1 << 0x1d) | (1 << 0x1e) | (1 << 0x1f),
-	},
-	[LAW_TRGT_IF_PCIE_2] = {
-		.cfg =   (1 << 1) | (1 << 6) | (1 << 7) | (1 << 9) |
-			 (1 << 0xd) | (1 << 0x15) | (1 << 0x16) | (1 << 0x17) |
-			 (1 << 0x18) | (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b),
-	},
-	[LAW_TRGT_IF_PCIE_3] = {
-		.cfg =   (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) | (1 << 9) |
-			 (1 << 0xa) | (1 << 0xb) | (1 << 0xd) | (1 << 0x15) |
-			 (1 << 0x16) | (1 << 0x17) | (1 << 0x18) | (1 << 0x1c),
-	},
-};
-#elif defined(CONFIG_P2010) || defined(CONFIG_P2020)
-static struct pci_info pci_config_info[] =
-{
-	[LAW_TRGT_IF_PCIE_1] = {
-		.cfg =   (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6) |
-			 (1 << 0xd) | (1 << 0xe) | (1 << 0xf),
-	},
-	[LAW_TRGT_IF_PCIE_2] = {
-		.cfg =   (1 << 2) | (1 << 0xe),
-	},
-	[LAW_TRGT_IF_PCIE_3] = {
-		.cfg =   (1 << 2) | (1 << 4),
-	},
-};
-#elif defined(CONFIG_FSL_CORENET)
-#else
-#error Need to define pci_config_info for processor
-#endif
-
-#ifndef CONFIG_FSL_CORENET
-int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel)
-{
-	return ((1 << io_sel) & pci_config_info[trgt].cfg);
-}
-#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
new file mode 100644
index 0000000000..e46d328067
--- /dev/null
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+
+#if defined(CONFIG_FSL_CORENET)
+	#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
+	#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
+	#define _DEVDISR_RMU   FSL_CORENET_DEVDISR_RMU
+	#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+#elif defined(CONFIG_MPC85xx)
+	#define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
+	#define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
+	#define _DEVDISR_RMU   MPC85xx_DEVDISR_RMSG
+	#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+#elif defined(CONFIG_MPC86xx)
+	#define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
+	#define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
+	#define _DEVDISR_RMU   MPC86xx_DEVDISR_RMSG
+	#define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
+		(&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
+#else
+#error "No defines for DEVDISR_SRIO"
+#endif
+
+void srio_init(void)
+{
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
+	int srio1_used = 0, srio2_used = 0;
+
+	if (is_serdes_configured(SRIO1)) {
+		set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
+				law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
+				LAW_TRGT_IF_RIO_1);
+		srio1_used = 1;
+		printf("SRIO1: enabled\n");
+	} else {
+		printf("SRIO1: disabled\n");
+	}
+
+#ifdef CONFIG_SRIO2
+	if (is_serdes_configured(SRIO2)) {
+		set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS,
+				law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE),
+				LAW_TRGT_IF_RIO_2);
+		srio2_used = 1;
+		printf("SRIO2: enabled\n");
+	} else {
+		printf("SRIO2: disabled\n");
+	}
+#endif
+
+#ifdef CONFIG_FSL_CORENET
+	/* On FSL_CORENET devices we can disable individual ports */
+	if (!srio1_used)
+		setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1);
+	if (!srio2_used)
+		setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2);
+#endif
+
+	/* neither port is used - disable everything */
+	if (!srio1_used && !srio2_used) {
+		setbits_be32(&gur->devdisr, _DEVDISR_SRIO1);
+		setbits_be32(&gur->devdisr, _DEVDISR_SRIO2);
+		setbits_be32(&gur->devdisr, _DEVDISR_RMU);
+	}
+}