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| author | Becky Bruce <beckyb@kernel.crashing.org> | 2010-06-17 11:37:20 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-07-16 10:55:09 -0500 |
| commit | f51cdaf19141151ce2b40d562a468605340f2315 (patch) | |
| tree | 60b51af79796f061d119f2839d101f9584964dfc /arch/powerpc/cpu/mpc85xx/speed.c | |
| parent | 0914f4832887341ee073d2d2bfbada69a6872548 (diff) | |
| download | blackbird-obmc-uboot-f51cdaf19141151ce2b40d562a468605340f2315.tar.gz blackbird-obmc-uboot-f51cdaf19141151ce2b40d562a468605340f2315.zip | |
83xx/85xx/86xx: LBC register cleanup
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers. Merge
this into a single spot.
To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.
In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.
I have done a successful ppc build all and tested a board or two from
each processor family.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/speed.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/speed.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 8132115fca..dd4c6b3e98 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -172,10 +172,7 @@ void get_sys_info (sys_info_t * sysInfo) /* We will program LCRR to this value later */ lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; #else - { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); - lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV; - } + lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; #endif if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { #if defined(CONFIG_FSL_CORENET) |
