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| author | York Sun <yorksun@freescale.com> | 2014-03-28 15:07:27 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-04-22 17:58:48 -0700 |
| commit | c3678b0937a0543280067fd8e08e6e2d278d90e2 (patch) | |
| tree | 166623230c6ec5a618c800b4cbc52d56e101984b /arch/powerpc/cpu/mpc85xx/speed.c | |
| parent | 22cbf964345e502afa29087c343db309831ab111 (diff) | |
| download | blackbird-obmc-uboot-c3678b0937a0543280067fd8e08e6e2d278d90e2.tar.gz blackbird-obmc-uboot-c3678b0937a0543280067fd8e08e6e2d278d90e2.zip | |
powerpc/mpc85xx: Add workaround for erratum A007212
Erratum A007212 for DDR is about a runaway condition for DDR PLL
oscilliator. Please refer to erratum document for detail.
For this workaround to work, DDR PLL needs to be disabled in RCW.
However, u-boot needs to know the expected PLL ratio. We put the
ratio in a reserved field RCW[18:23]. U-boot will skip this workaround
if DDR PLL ratio is set, or the reserved field is not set.
Workaround for erratum A007212 applies to selected versions of
B4/T4 SoCs. It is safe to apply the workaround to all versions. It
is helpful for upgrading SoC without changing u-boot. In case DDR
PLL is disabled by RCW (part of the erratum workaround), we need this
u-boot workround to bring up DDR clock.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/speed.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/speed.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 488fd5ea76..35dfb0a9a9 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -107,6 +107,13 @@ void get_sys_info(sys_info_t *sys_info) mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 + if (mem_pll_rat == 0) { + mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> + FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & + FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + } +#endif /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 * it uses 6. |
