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| author | Paul Burton <paul.burton@imgtec.com> | 2015-01-29 01:27:58 +0000 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2015-01-29 12:55:01 +0100 |
| commit | 4a5d8898bca3e442b61e34b811aec8332752efd3 (patch) | |
| tree | e51ad11b501325113b0d0e58756acfbcb523b111 /arch/mips/cpu/mips32/Makefile | |
| parent | 30374f98d14d5979f95a9d21d66346eaa9a795a1 (diff) | |
| download | blackbird-obmc-uboot-4a5d8898bca3e442b61e34b811aec8332752efd3.tar.gz blackbird-obmc-uboot-4a5d8898bca3e442b61e34b811aec8332752efd3.zip | |
MIPS: unify cache initialization code
The mips32 & mips64 cache initialization code differs only in that the
mips32 code supports reading the cache size from coprocessor 0 registers
at runtime. Move the more developed mips32 version to a common
arch/mips/lib/cache_init.S & remove the now-redundant mips64 version in
order to reduce duplication. The temporary registers used are shuffled
slightly in order to work for both mips32 & mips64 builds. The RA
register is defined differently to suit mips32 & mips64, but will be
removed by a later commit in the series after further cleanup.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'arch/mips/cpu/mips32/Makefile')
| -rw-r--r-- | arch/mips/cpu/mips32/Makefile | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/mips/cpu/mips32/Makefile b/arch/mips/cpu/mips32/Makefile index fa82dd375f..19d316ab75 100644 --- a/arch/mips/cpu/mips32/Makefile +++ b/arch/mips/cpu/mips32/Makefile @@ -6,7 +6,6 @@ # extra-y = start.o -obj-y = cache.o -obj-y += cpu.o interrupts.o time.o +obj-y = cpu.o interrupts.o time.o obj-$(CONFIG_SOC_AU1X00) += au1x00/ |
