microblaze: Add SPL support

Add support for U-BOOT SPL. NOR and RAM mode are supported.
There are 3 images in NOR flash. u-boot.img, dtb and kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

5 files changed, 132 insertions, 1 deletions

diff --git a/arch/microblaze/cpu/Makefile b/arch/microblaze/cpu/Makefile
index 6e201f2d54..4955e81236 100644
--- a/arch/microblaze/cpu/Makefile
+++ b/arch/microblaze/cpu/Makefile
@@ -8,3 +8,4 @@
 extra-y	= start.o
 obj-y	= irq.o
 obj-y	+= cpu.o interrupts.o cache.o exception.o timer.o
+obj-$(CONFIG_SPL_BUILD)	+= spl.o
diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c
new file mode 100644
index 0000000000..091226133e
--- /dev/null
+++ b/arch/microblaze/cpu/spl.c
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2013 - 2014 Xilinx, Inc
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <image.h>
+#include <spl.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+bool boot_linux;
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_NOR;
+}
+
+/* Board initialization after bss clearance */
+void spl_board_init(void)
+{
+	gd = (gd_t *)CONFIG_SPL_STACK_ADDR;
+
+	/* enable console uart printing */
+	preloader_console_init();
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+void __noreturn jump_to_image_linux(void *arg)
+{
+	debug("Entering kernel arg pointer: 0x%p\n", arg);
+	typedef void (*image_entry_arg_t)(char *, ulong, ulong)
+		__attribute__ ((noreturn));
+	image_entry_arg_t image_entry =
+		(image_entry_arg_t)spl_image.entry_point;
+
+	image_entry(NULL, 0, (ulong)arg);
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
+int spl_start_uboot(void)
+{
+#ifdef CONFIG_SPL_OS_BOOT
+	if (boot_linux)
+		return 0;
+#endif
+
+	return 1;
+}
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 8928024838..1757bbfa94 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -22,6 +22,11 @@ _start:
 	 */
 
 	mts	rmsr, r0	/* disable cache */
+
+#if defined(CONFIG_SPL_BUILD)
+	addi	r1, r0, CONFIG_SPL_STACK_ADDR
+	addi	r1, r1, -4	/* Decrement SP to top of memory */
+#else
 	addi	r1, r0, CONFIG_SYS_INIT_SP_OFFSET
 	addi	r1, r1, -4	/* Decrement SP to top of memory */
 
@@ -115,6 +120,7 @@ _start:
 	sh	r7, r0, r8
 	rsubi	r8, r10, 0x26
 	sh	r6, r0, r8
+#endif /* BUILD_SPL */
 
 	/* Flush cache before enable cache */
 	addik	r5, r0, 0
@@ -139,9 +145,14 @@ clear_bss:
 	cmp     r6, r5, r4 /* check if we have reach the end */
 	bnei    r6, 2b
 3:	/* jumping to board_init */
+#ifndef CONFIG_SPL_BUILD
 	brai	board_init_f
+#else
+	brai	board_init_r
+#endif
 1:	bri	1b
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * Read 16bit little endian
  */
@@ -174,3 +185,4 @@ out16:	bslli	r3, r6, 8
 	rtsd	r15, 8
 	or	r0, r0, r0
 	.end	out16
+#endif
diff --git a/arch/microblaze/cpu/timer.c b/arch/microblaze/cpu/timer.c
index 69ae6d4d87..3960bbb08a 100644
--- a/arch/microblaze/cpu/timer.c
+++ b/arch/microblaze/cpu/timer.c
@@ -34,6 +34,7 @@ void __udelay(unsigned long usec)
 	}
 }
 
+#ifndef CONFIG_SPL_BUILD
 static void timer_isr(void *arg)
 {
 	timestamp++;
@@ -62,10 +63,15 @@ int timer_init (void)
 		if (ret)
 			tmr = NULL;
 	}
-
 	/* No problem if timer is not found/initialized */
 	return 0;
 }
+#else
+int timer_init(void)
+{
+	return 0;
+}
+#endif
 
 /*
  * This function is derived from PowerPC code (read timebase as long long).
diff --git a/arch/microblaze/cpu/u-boot-spl.lds b/arch/microblaze/cpu/u-boot-spl.lds
new file mode 100644
index 0000000000..96353cd96c
--- /dev/null
+++ b/arch/microblaze/cpu/u-boot-spl.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2013 - 2014 Xilinx, Inc
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+
+OUTPUT_ARCH(microblaze)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text ALIGN(0x4):
+	{
+		__text_start = .;
+		arch/microblaze/cpu/start.o (.text)
+		*(.text)
+		*(.text.*)
+		__text_end = .;
+	}
+
+	.rodata ALIGN(0x4):
+	{
+		__rodata_start = .;
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+		__rodata_end = .;
+	}
+
+	.data ALIGN(0x4):
+	{
+		__data_start = .;
+		*(.data)
+		*(.data.*)
+		__data_end = .;
+	}
+
+	.bss ALIGN(0x4):
+	{
+		__bss_start = .;
+		*(.sbss)
+		*(.scommon)
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end = .;
+	}
+	__end = . ;
+}
+
+#if defined(CONFIG_SPL_MAX_FOOTPRINT)
+ASSERT(__end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \
+        "SPL image plus BSS too big");
+#endif