Merge branch 'rmobile' of git://git.denx.de/u-boot-sh

7 files changed, 215 insertions, 0 deletions

diff --git a/arch/arm/include/asm/arch-rmobile/mmc.h b/arch/arm/include/asm/arch-rmobile/mmc.h
new file mode 100644
index 0000000000..4e0fef1198
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/mmc.h
@@ -0,0 +1,14 @@
+/*
+ * Renesas SuperH MMCIF driver.
+ *
+ * Copyright (C)  2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C)  2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef _RMOBILE_MMC_H_
+#define _RMOBILE_MMC_H_
+
+int mmcif_mmc_init(void);
+
+#endif /* _RMOBILE_MMC_H_ */
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790.h b/arch/arm/include/asm/arch-rmobile/r8a7790.h
index de1486933a..132d58c117 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7790.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7790.h
@@ -15,6 +15,19 @@
 #define CONFIG_SYS_I2C_SH_BASE2	0xE6520000
 #define CONFIG_SYS_I2C_SH_BASE3	0xE60B0000
 
+/* Module stop control/status register bits */
+#define MSTP0_BITS	0x00640801
+#define MSTP1_BITS	0xDB6E9BDF
+#define MSTP2_BITS	0x300DA1FC
+#define MSTP3_BITS	0xF08CF831
+#define MSTP4_BITS	0x80000184
+#define MSTP5_BITS	0x44C00046
+#define MSTP7_BITS	0x07F30718
+#define MSTP8_BITS	0x01F0FF84
+#define MSTP9_BITS	0xF5979FCF
+#define MSTP10_BITS	0xFFFEFFE0
+#define MSTP11_BITS	0x00000000
+
 #define R8A7790_CUT_ES2X	2
 #define IS_R8A7790_ES2()	\
 	(rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h
index 26a0bd58ff..d2cbcd761d 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7791.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h
@@ -51,6 +51,19 @@
 #define DBSC3_1_QOS_W15_BASE	0xE67A2F00
 #define DBSC3_1_DBADJ2		0xE67A00C8
 
+/* Module stop control/status register bits */
+#define MSTP0_BITS	0x00640801
+#define MSTP1_BITS	0x9B6C9B5A
+#define MSTP2_BITS	0x100D21FC
+#define MSTP3_BITS	0xF08CD810
+#define MSTP4_BITS	0x800001C4
+#define MSTP5_BITS	0x44C00046
+#define MSTP7_BITS	0x05BFE618
+#define MSTP8_BITS	0x40C0FE85
+#define MSTP9_BITS	0xFF979FFF
+#define MSTP10_BITS	0xFFFEFFE0
+#define MSTP11_BITS	0x000001C0
+
 #define R8A7791_CUT_ES2X	2
 #define IS_R8A7791_ES2()	\
 	(rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X)
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7793.h b/arch/arm/include/asm/arch-rmobile/r8a7793.h
index 778812ee84..1abdeb7450 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7793.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7793.h
@@ -56,6 +56,20 @@
 /*
  * R8A7793 I/O Product Information
  */
+
+/* Module stop control/status register bits */
+#define MSTP0_BITS	0x00640801
+#define MSTP1_BITS	0x9B6C9B5A
+#define MSTP2_BITS	0x100D21FC
+#define MSTP3_BITS	0xF08CD810
+#define MSTP4_BITS	0x800001C4
+#define MSTP5_BITS	0x44C00046
+#define MSTP7_BITS	0x05BFE618
+#define MSTP8_BITS	0x40C0FE85
+#define MSTP9_BITS	0xFF979FFF
+#define MSTP10_BITS	0xFFFEFFE0
+#define MSTP11_BITS	0x000001C0
+
 #define R8A7793_CUT_ES2X	2
 #define IS_R8A7793_ES2() \
 	(rmobile_get_cpu_rev_integer() == R8A7793_CUT_ES2X)
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7794.h b/arch/arm/include/asm/arch-rmobile/r8a7794.h
index 66d5a29d5f..d7c9004772 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7794.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7794.h
@@ -14,4 +14,17 @@
 /* SH-I2C */
 #define CONFIG_SYS_I2C_SH_BASE2	0xE60B0000
 
+/* Module stop control/status register bits */
+#define MSTP0_BITS	0x00440801
+#define MSTP1_BITS	0x936899DA
+#define MSTP2_BITS	0x100D21FC
+#define MSTP3_BITS	0xE084D810
+#define MSTP4_BITS	0x800001C4
+#define MSTP5_BITS	0x40C00044
+#define MSTP7_BITS	0x013FE618
+#define MSTP8_BITS	0x40803C05
+#define MSTP9_BITS	0xFB879FEE
+#define MSTP10_BITS	0xFFFEFFE0
+#define MSTP11_BITS	0x000001C0
+
 #endif /* __ASM_ARCH_R8A7794_H */
diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h
index dbbebcf361..23c4bba6ed 100644
--- a/arch/arm/include/asm/arch-rmobile/rcar-base.h
+++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h
@@ -29,6 +29,45 @@
 #define SCIF4_BASE		0xE6EE0000
 #define SCIF5_BASE		0xE6EE8000
 
+/* Module stop status register */
+#define MSTPSR0			0xE6150030
+#define MSTPSR1			0xE6150038
+#define MSTPSR2			0xE6150040
+#define MSTPSR3			0xE6150048
+#define MSTPSR4			0xE615004C
+#define MSTPSR5			0xE615003C
+#define MSTPSR7			0xE61501C4
+#define MSTPSR8			0xE61509A0
+#define MSTPSR9			0xE61509A4
+#define MSTPSR10		0xE61509A8
+#define MSTPSR11		0xE61509AC
+
+/* Realtime module stop control register */
+#define RMSTPCR0		0xE6150110
+#define RMSTPCR1		0xE6150114
+#define RMSTPCR2		0xE6150118
+#define RMSTPCR3		0xE615011C
+#define RMSTPCR4		0xE6150120
+#define RMSTPCR5		0xE6150124
+#define RMSTPCR7		0xE615012C
+#define RMSTPCR8		0xE6150980
+#define RMSTPCR9		0xE6150984
+#define RMSTPCR10		0xE6150988
+#define RMSTPCR11		0xE615098C
+
+/* System module stop control register */
+#define SMSTPCR0		0xE6150130
+#define SMSTPCR1		0xE6150134
+#define SMSTPCR2		0xE6150138
+#define SMSTPCR3		0xE615013C
+#define SMSTPCR4		0xE6150140
+#define SMSTPCR5		0xE6150144
+#define SMSTPCR7		0xE615014C
+#define SMSTPCR8		0xE6150990
+#define SMSTPCR9		0xE6150994
+#define SMSTPCR10		0xE6150998
+#define SMSTPCR11		0xE615099C
+
 /*
  * SH-I2C
  * Ch2 and ch3 are different address. These are defined
diff --git a/arch/arm/include/asm/arch-rmobile/rcar-mstp.h b/arch/arm/include/asm/arch-rmobile/rcar-mstp.h
new file mode 100644
index 0000000000..9a564f892c
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/rcar-mstp.h
@@ -0,0 +1,109 @@
+/*
+ * arch/arm/include/asm/arch-rmobile/rcar-mstp.h
+ *
+ * Copyright (C) 2013, 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2013, 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_RCAR_MSTP_H
+#define __ASM_ARCH_RCAR_MSTP_H
+
+#define mstp_setbits(type, addr, saddr, set) \
+		out_##type((saddr), in_##type(addr) | (set))
+#define mstp_clrbits(type, addr, saddr, clear) \
+		out_##type((saddr), in_##type(addr) & ~(clear))
+#define mstp_setclrbits(type, addr, set, clear) \
+		out_##type((addr), (in_##type(addr) | (set)) & ~(clear))
+#define mstp_setbits_le32(addr, saddr, set) \
+		mstp_setbits(le32, addr, saddr, set)
+#define mstp_clrbits_le32(addr, saddr, clear) \
+		mstp_clrbits(le32, addr, saddr, clear)
+#define mstp_setclrbits_le32(addr, set, clear) \
+		mstp_setclrbits(le32, addr, set, clear)
+
+#ifndef CONFIG_SMSTP0_ENA
+#define CONFIG_SMSTP0_ENA	0x00
+#endif
+#ifndef CONFIG_SMSTP1_ENA
+#define CONFIG_SMSTP1_ENA	0x00
+#endif
+#ifndef CONFIG_SMSTP2_ENA
+#define CONFIG_SMSTP2_ENA	0x00
+#endif
+#ifndef CONFIG_SMSTP3_ENA
+#define CONFIG_SMSTP3_ENA	0x00
+#endif
+#ifndef CONFIG_SMSTP4_ENA
+#define CONFIG_SMSTP4_ENA	0x00
+#endif
+#ifndef CONFIG_SMSTP5_ENA
+#define CONFIG_SMSTP5_ENA	0x00
+#endif
+#ifndef CONFIG_SMSTP6_ENA
+#define CONFIG_SMSTP6_ENA	0x00
+#endif
+#ifndef CONFIG_SMSTP7_ENA
+#define CONFIG_SMSTP7_ENA	0x00
+#endif
+#ifndef CONFIG_SMSTP8_ENA
+#define CONFIG_SMSTP8_ENA	0x00
+#endif
+#ifndef CONFIG_SMSTP9_ENA
+#define CONFIG_SMSTP9_ENA	0x00
+#endif
+#ifndef CONFIG_SMSTP10_ENA
+#define CONFIG_SMSTP10_ENA	0x00
+#endif
+#ifndef CONFIG_SMSTP11_ENA
+#define CONFIG_SMSTP11_ENA	0x00
+#endif
+
+#ifndef CONFIG_RMSTP0_ENA
+#define CONFIG_RMSTP0_ENA	0x00
+#endif
+#ifndef CONFIG_RMSTP1_ENA
+#define CONFIG_RMSTP1_ENA	0x00
+#endif
+#ifndef CONFIG_RMSTP2_ENA
+#define CONFIG_RMSTP2_ENA	0x00
+#endif
+#ifndef CONFIG_RMSTP3_ENA
+#define CONFIG_RMSTP3_ENA	0x00
+#endif
+#ifndef CONFIG_RMSTP4_ENA
+#define CONFIG_RMSTP4_ENA	0x00
+#endif
+#ifndef CONFIG_RMSTP5_ENA
+#define CONFIG_RMSTP5_ENA	0x00
+#endif
+#ifndef CONFIG_RMSTP6_ENA
+#define CONFIG_RMSTP6_ENA	0x00
+#endif
+#ifndef CONFIG_RMSTP7_ENA
+#define CONFIG_RMSTP7_ENA	0x00
+#endif
+#ifndef CONFIG_RMSTP8_ENA
+#define CONFIG_RMSTP8_ENA	0x00
+#endif
+#ifndef CONFIG_RMSTP9_ENA
+#define CONFIG_RMSTP9_ENA	0x00
+#endif
+#ifndef CONFIG_RMSTP10_ENA
+#define CONFIG_RMSTP10_ENA	0x00
+#endif
+#ifndef CONFIG_RMSTP11_ENA
+#define CONFIG_RMSTP11_ENA	0x00
+#endif
+
+struct mstp_ctl {
+	u32 s_addr;
+	u32 s_dis;
+	u32 s_ena;
+	u32 r_addr;
+	u32 r_dis;
+	u32 r_ena;
+};
+
+#endif /* __ASM_ARCH_RCAR_MSTP_H */