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authorTom Rini <trini@ti.com>2014-11-04 07:00:48 -0500
committerTom Rini <trini@ti.com>2014-11-04 07:00:48 -0500
commitccc39d66c3c8381690fcfffb794768c55c909460 (patch)
tree70249376d64f734ab928734640001e6aa4596e9f /arch/arm
parent4dc949266da6f55ef221e53c637150252b6ac35a (diff)
parent4aa97312f7147b68b8b7c731d7bb01cff8dda2d6 (diff)
downloadblackbird-obmc-uboot-ccc39d66c3c8381690fcfffb794768c55c909460.tar.gz
blackbird-obmc-uboot-ccc39d66c3c8381690fcfffb794768c55c909460.zip
Merge branch 'master' of git://git.denx.de/u-boot-samsung
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/include/asm/arch-exynos/cpu.h9
-rw-r--r--arch/arm/include/asm/arch-exynos/gpio.h59
2 files changed, 48 insertions, 20 deletions
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index ba717146f5..78aceef17b 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -29,6 +29,8 @@
#define EXYNOS4_MIU_BASE 0x10600000
#define EXYNOS4_ACE_SFR_BASE 0x10830000
#define EXYNOS4_GPIO_PART2_BASE 0x11000000
+#define EXYNOS4_GPIO_PART2_0 0x11000000 /* GPJ0 */
+#define EXYNOS4_GPIO_PART2_1 0x11000c00 /* GPX0 */
#define EXYNOS4_GPIO_PART1_BASE 0x11400000
#define EXYNOS4_FIMD_BASE 0x11C00000
#define EXYNOS4_MIPI_DSIM_BASE 0x11C80000
@@ -70,7 +72,14 @@
#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000
#define EXYNOS4X12_ACE_SFR_BASE 0x10830000
#define EXYNOS4X12_GPIO_PART2_BASE 0x11000000
+#define EXYNOS4X12_GPIO_PART2_0 0x11000000
+#define EXYNOS4X12_GPIO_PART2_1 0x11000040 /* GPK0 */
+#define EXYNOS4X12_GPIO_PART2_2 0x11000260 /* GPM0 */
+#define EXYNOS4X12_GPIO_PART2_3 0x11000c00 /* GPX0 */
#define EXYNOS4X12_GPIO_PART1_BASE 0x11400000
+#define EXYNOS4X12_GPIO_PART1_0 0x11400000 /* GPA0 */
+#define EXYNOS4X12_GPIO_PART1_1 0x11400180 /* GPF0 */
+#define EXYNOS4X12_GPIO_PART1_2 0x11400240 /* GPJ0 */
#define EXYNOS4X12_FIMD_BASE 0x11C00000
#define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000
#define EXYNOS4X12_USBOTG_BASE 0x12480000
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index ad2ece64f4..02287decc2 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -284,7 +284,10 @@ enum exynos4_gpio_pin {
EXYNOS4_GPIO_Y65,
EXYNOS4_GPIO_Y66,
EXYNOS4_GPIO_Y67,
- EXYNOS4_GPIO_X00, /* 256 0x100 */
+
+ /* GPIO_PART2_1 STARTS */
+ EXYNOS4_GPIO_MAX_PORT_PART_2_0, /* 256 0x100 */
+ EXYNOS4_GPIO_X00 = EXYNOS4_GPIO_MAX_PORT_PART_2_0,
EXYNOS4_GPIO_X01,
EXYNOS4_GPIO_X02,
EXYNOS4_GPIO_X03,
@@ -318,8 +321,8 @@ enum exynos4_gpio_pin {
EXYNOS4_GPIO_X37,
/* GPIO_PART3_STARTS */
- EXYNOS4_GPIO_MAX_PORT_PART_2, /* 288 0x120 */
- EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2,
+ EXYNOS4_GPIO_MAX_PORT_PART_2_1, /* 288 0x120 */
+ EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2_1,
EXYNOS4_GPIO_Z1,
EXYNOS4_GPIO_Z2,
EXYNOS4_GPIO_Z3,
@@ -332,7 +335,7 @@ enum exynos4_gpio_pin {
};
enum exynos4X12_gpio_pin {
- /* GPIO_PART1_STARTS */
+ /* EXYNOS4X12_GPIO_PART1_0 starts here */
EXYNOS4X12_GPIO_A00, /* 0 */
EXYNOS4X12_GPIO_A01,
EXYNOS4X12_GPIO_A02,
@@ -389,7 +392,9 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_D15,
EXYNOS4X12_GPIO_D16,
EXYNOS4X12_GPIO_D17,
- EXYNOS4X12_GPIO_F00, /* 56 0x38 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, /* 56 0x38 */
+ /* EXYNOS4X12_GPIO_PART1_1 starts here */
+ EXYNOS4X12_GPIO_F00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_0,
EXYNOS4X12_GPIO_F01,
EXYNOS4X12_GPIO_F02,
EXYNOS4X12_GPIO_F03,
@@ -421,7 +426,9 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_F35,
EXYNOS4X12_GPIO_F36,
EXYNOS4X12_GPIO_F37,
- EXYNOS4X12_GPIO_J00, /* 88 0x58 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, /* 88 0x58 */
+ /* EXYNOS4X12_GPIO_PART1_2 starts here */
+ EXYNOS4X12_GPIO_J00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_1,
EXYNOS4X12_GPIO_J01,
EXYNOS4X12_GPIO_J02,
EXYNOS4X12_GPIO_J03,
@@ -438,9 +445,12 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_J16,
EXYNOS4X12_GPIO_J17,
- /* GPIO_PART2_STARTS */
- EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 104 0x66 */
- EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1,
+ /**
+ * EXYNOS4X12_GPIO_PART2_0 is not used
+ * EXYNOS4X12_GPIO_PART2_1 starts here
+ */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, /* 104 0x66 */
+ EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_2,
EXYNOS4X12_GPIO_K01,
EXYNOS4X12_GPIO_K02,
EXYNOS4X12_GPIO_K03,
@@ -552,7 +562,9 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_Y65,
EXYNOS4X12_GPIO_Y66,
EXYNOS4X12_GPIO_Y67,
- EXYNOS4X12_GPIO_M00, /* 216 0xd8 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, /* 216 0xd8 */
+ /* EXYNOS4X12_GPIO_PART2_2 starts here */
+ EXYNOS4X12_GPIO_M00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_1,
EXYNOS4X12_GPIO_M01,
EXYNOS4X12_GPIO_M02,
EXYNOS4X12_GPIO_M03,
@@ -592,7 +604,9 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_M45,
EXYNOS4X12_GPIO_M46,
EXYNOS4X12_GPIO_M47,
- EXYNOS4X12_GPIO_X00, /* 256 0x100 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, /* 256 0x100 */
+ /* EXYNOS4X12_GPIO_PART2_3 starts here */
+ EXYNOS4X12_GPIO_X00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_2,
EXYNOS4X12_GPIO_X01,
EXYNOS4X12_GPIO_X02,
EXYNOS4X12_GPIO_X03,
@@ -625,9 +639,9 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_X36,
EXYNOS4X12_GPIO_X37,
- /* GPIO_PART3_STARTS */
- EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 288 0x120 */
- EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2,
+ /* EXYNOS4X12_GPIO_PART3 starts here */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, /* 288 0x120 */
+ EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_3,
EXYNOS4X12_GPIO_Z1,
EXYNOS4X12_GPIO_Z2,
EXYNOS4X12_GPIO_Z3,
@@ -636,7 +650,7 @@ enum exynos4X12_gpio_pin {
EXYNOS4X12_GPIO_Z6,
EXYNOS4X12_GPIO_Z7,
- /* GPIO_PART4_STARTS */
+ /* EXYNOS4X12_GPIO_PART4 starts here */
EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */
EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3,
EXYNOS4X12_GPIO_V01,
@@ -1339,17 +1353,22 @@ struct gpio_info {
unsigned int max_gpio; /* Maximum GPIO in this part */
};
-#define EXYNOS4_GPIO_NUM_PARTS 3
+#define EXYNOS4_GPIO_NUM_PARTS 4
static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = {
{ EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 },
- { EXYNOS4_GPIO_PART2_BASE, EXYNOS4_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS4_GPIO_PART2_0, EXYNOS4_GPIO_MAX_PORT_PART_2_0 },
+ { EXYNOS4_GPIO_PART2_1, EXYNOS4_GPIO_MAX_PORT_PART_2_1 },
{ EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT },
};
-#define EXYNOS4X12_GPIO_NUM_PARTS 4
+#define EXYNOS4X12_GPIO_NUM_PARTS 8
static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = {
- { EXYNOS4X12_GPIO_PART1_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_1 },
- { EXYNOS4X12_GPIO_PART2_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS4X12_GPIO_PART1_0, EXYNOS4X12_GPIO_MAX_PORT_PART_1_0 },
+ { EXYNOS4X12_GPIO_PART1_1, EXYNOS4X12_GPIO_MAX_PORT_PART_1_1 },
+ { EXYNOS4X12_GPIO_PART1_2, EXYNOS4X12_GPIO_MAX_PORT_PART_1_2 },
+ { EXYNOS4X12_GPIO_PART2_1, EXYNOS4X12_GPIO_MAX_PORT_PART_2_1 },
+ { EXYNOS4X12_GPIO_PART2_2, EXYNOS4X12_GPIO_MAX_PORT_PART_2_2 },
+ { EXYNOS4X12_GPIO_PART2_3, EXYNOS4X12_GPIO_MAX_PORT_PART_2_3 },
{ EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 },
{ EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT },
};
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