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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-26 14:21:38 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-29 03:50:16 +0900 |
| commit | 00dd3f6ab068276f8baa409e9317fbf466187a34 (patch) | |
| tree | bdc2a6417b93553f6c641d77bc7e5fd7547364e8 /arch/arm/mach-uniphier/dram/umc-ph1-sld8.c | |
| parent | 94b756f3318b5dea3c1aefa670f43ae85d780144 (diff) | |
| download | blackbird-obmc-uboot-00dd3f6ab068276f8baa409e9317fbf466187a34.tar.gz blackbird-obmc-uboot-00dd3f6ab068276f8baa409e9317fbf466187a34.zip | |
ARM: uniphier: remove UMC_INITCTL* and UMC_DRMR* settings
These settings were used only for the PH1-sLD3 and older SoCs. The
PH1-LD4 and newer one just ignore them because their DDR-PHY take
care of such timing parameters instead.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/dram/umc-ph1-sld8.c')
| -rw-r--r-- | arch/arm/mach-uniphier/dram/umc-ph1-sld8.c | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index 3c2724eb37..fa0619fc72 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c @@ -58,24 +58,6 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, writel(0x16958924, dramcont + UMC_CMDCTLB); #endif - writel(0x5101046A, dramcont + UMC_INITCTLA); - - if (size == 1) - writel(0x27028B0A, dramcont + UMC_INITCTLB); - else if (size == 2) - writel(0x38028B0A, dramcont + UMC_INITCTLB); - - writel(0x00FF00FF, dramcont + UMC_INITCTLC); - writel(0x00000b51, dramcont + UMC_DRMMR0); - writel(0x00000006, dramcont + UMC_DRMMR1); - writel(0x00000290, dramcont + UMC_DRMMR2); - -#ifdef CONFIG_DDR_STANDARD - writel(0x00000000, dramcont + UMC_DRMMR3); -#else - writel(0x00000800, dramcont + UMC_DRMMR3); -#endif - if (size == 1) writel(0x00240512, dramcont + UMC_SPCCTLA); else if (size == 2) |
