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author | Thomas Abraham <thomas.ab@samsung.com> | 2015-08-03 17:58:00 +0530 |
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committer | Minkyu Kang <mk7.kang@samsung.com> | 2015-08-17 13:06:52 +0900 |
commit | 77b55e8cfcee9ce1a973bf4dad3e160dd0be01f3 (patch) | |
tree | 0ec9071faf7ea93eca773777c989f1da65aada24 /arch/arm/mach-exynos/include/mach/clk.h | |
parent | 632093b566569329bc6e5b0893bdca01de905314 (diff) | |
download | blackbird-obmc-uboot-77b55e8cfcee9ce1a973bf4dad3e160dd0be01f3.tar.gz blackbird-obmc-uboot-77b55e8cfcee9ce1a973bf4dad3e160dd0be01f3.zip |
ARM: exynos: move SoC sources to mach-exynos
Move arch/arm/cpu/armv7/exynos/* to arch/arm/mach-exynos/* to allow
reuse of existing code for ARMv8 based Exynos platforms.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos/include/mach/clk.h')
-rw-r--r-- | arch/arm/mach-exynos/include/mach/clk.h | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/include/mach/clk.h b/arch/arm/mach-exynos/include/mach/clk.h new file mode 100644 index 0000000000..d20b7d2ae3 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/clk.h @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2010 Samsung Electronics + * Minkyu Kang <mk7.kang@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARM_ARCH_CLK_H_ +#define __ASM_ARM_ARCH_CLK_H_ + +#define APLL 0 +#define MPLL 1 +#define EPLL 2 +#define HPLL 3 +#define VPLL 4 +#define BPLL 5 +#define RPLL 6 +#define SPLL 7 +#define CPLL 8 +#define DPLL 9 +#define IPLL 10 + +#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8)) +#define MASK_RATIO(x) (0xf << (x << 4)) +#define SET_PRE_RATIO(x, y) ((y & 0xff) << ((x << 4) + 8)) +#define SET_RATIO(x, y) ((y & 0xf) << (x << 4)) + +enum pll_src_bit { + EXYNOS_SRC_MPLL = 6, + EXYNOS_SRC_EPLL, + EXYNOS_SRC_VPLL, + EXYNOS542X_SRC_MPLL = 3, + EXYNOS542X_SRC_SPLL, + EXYNOS542X_SRC_EPLL = 6, + EXYNOS542X_SRC_RPLL, +}; + +unsigned long get_pll_clk(int pllreg); +unsigned long get_arm_clk(void); +unsigned long get_i2c_clk(void); +unsigned long get_pwm_clk(void); +unsigned long get_uart_clk(int dev_index); +unsigned long get_mmc_clk(int dev_index); +void set_mmc_clk(int dev_index, unsigned int div); +unsigned long get_lcd_clk(void); +void set_lcd_clk(void); +void set_mipi_clk(void); +int set_i2s_clk_source(unsigned int i2s_id); +int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq, + unsigned int i2s_id); +int set_epll_clk(unsigned long rate); +int set_spi_clk(int periph_id, unsigned int rate); + +/** + * get the clk frequency of the required peripheral + * + * @param peripheral Peripheral id + * + * @return frequency of the peripheral clk + */ +unsigned long clock_get_periph_rate(int peripheral); + +#endif |