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| author | Peng Fan <Peng.Fan@freescale.com> | 2014-12-31 11:01:38 +0800 |
|---|---|---|
| committer | Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> | 2014-12-31 14:52:32 +0530 |
| commit | b93ab2ee751a4a0231330a89e2f2f29963b434d0 (patch) | |
| tree | ff1294c78d954dbe2ffcb006bcc9dc21552eb347 /arch/arm/include | |
| parent | ed0c81c654209a2af71393e8756d94c7e944646b (diff) | |
| download | blackbird-obmc-uboot-b93ab2ee751a4a0231330a89e2f2f29963b434d0.tar.gz blackbird-obmc-uboot-b93ab2ee751a4a0231330a89e2f2f29963b434d0.zip | |
arm:mx6sx add QSPI support
Add QSPI support for mx6solox.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/clock.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 12 |
2 files changed, 7 insertions, 6 deletions
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 226a4cde17..a6de5ee4bc 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -67,5 +67,6 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num); void enable_ipu_clock(void); int enable_fec_anatop_clock(enum enet_freq freq); void enable_enet_clk(unsigned char enable); +void enable_qspi_clk(int qspi_num); void enable_thermal_clk(void); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5314298a1d..c968600b77 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -92,10 +92,10 @@ #define AIPS3_END_ADDR 0x022FFFFF #define WEIM_ARB_BASE_ADDR 0x50000000 #define WEIM_ARB_END_ADDR 0x57FFFFFF -#define QSPI1_ARB_BASE_ADDR 0x60000000 -#define QSPI1_ARB_END_ADDR 0x6FFFFFFF -#define QSPI2_ARB_BASE_ADDR 0x70000000 -#define QSPI2_ARB_END_ADDR 0x7FFFFFFF +#define QSPI0_AMBA_BASE 0x60000000 +#define QSPI0_AMBA_END 0x6FFFFFFF +#define QSPI1_AMBA_BASE 0x70000000 +#define QSPI1_AMBA_END 0x7FFFFFFF #else #define SATA_ARB_BASE_ADDR 0x02200000 #define SATA_ARB_END_ADDR 0x02203FFF @@ -262,8 +262,8 @@ #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) #ifdef CONFIG_MX6SX #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) -#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) -#define QSPI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) +#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) +#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) #else #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) |
