diff options
| author | Hao Zhang <hzhang@ti.com> | 2014-10-22 16:32:32 +0300 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-10-23 11:27:05 -0400 |
| commit | b66604fb66c3e8fee5d294ac548d6da52fd1fae1 (patch) | |
| tree | 5f46eae2a3a3051134a8932dbe7dc7a2757940b8 /arch/arm/include | |
| parent | 5ec66b140afff89c3ee5abde4a9eb4c0963c918c (diff) | |
| download | blackbird-obmc-uboot-b66604fb66c3e8fee5d294ac548d6da52fd1fae1.tar.gz blackbird-obmc-uboot-b66604fb66c3e8fee5d294ac548d6da52fd1fae1.zip | |
keystone2: enable OSR clock domain for K2L SoC
This patches enables the On-chip Shared Ram clock domain for K2L SoC.
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-keystone/hardware-k2l.h | 24 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-keystone/hardware.h | 1 |
2 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h b/arch/arm/include/asm/arch-keystone/hardware-k2l.h index c1fa3afa9d..05532ada70 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2l.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h @@ -60,6 +60,30 @@ #define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 #define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D +/* OSR */ +#define KS2_OSR_DATA_BASE 0x70000000 /* OSR data base */ +#define KS2_OSR_CFG_BASE 0x02348c00 /* OSR config base */ +#define KS2_OSR_ECC_VEC 0x08 /* ECC Vector reg */ +#define KS2_OSR_ECC_CTRL 0x14 /* ECC control reg */ + +/* OSR ECC Vector register */ +#define KS2_OSR_ECC_VEC_TRIG_RD BIT(15) /* trigger a read op */ +#define KS2_OSR_ECC_VEC_RD_DONE BIT(24) /* read complete */ + +#define KS2_OSR_ECC_VEC_RAM_ID_SH 0 /* RAM ID shift */ +#define KS2_OSR_ECC_VEC_RD_ADDR_SH 16 /* read address shift */ + +/* OSR ECC control register */ +#define KS2_OSR_ECC_CTRL_EN BIT(0) /* ECC enable bit */ +#define KS2_OSR_ECC_CTRL_CHK BIT(1) /* ECC check bit */ +#define KS2_OSR_ECC_CTRL_RMW BIT(2) /* ECC check bit */ + +/* Number of OSR RAM banks */ +#define KS2_OSR_NUM_RAM_BANKS 4 + +/* OSR memory size */ +#define KS2_OSR_SIZE 0x100000 + /* Number of DSP cores */ #define KS2_NUM_DSPS 4 diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index 295c6b0ea9..08a7c70038 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -142,6 +142,7 @@ typedef volatile unsigned int *dv_reg_p; /* MSMC control */ #define KS2_MSMC_CTRL_BASE 0x0bc00000 +#define KS2_MSMC_DATA_BASE 0x0c000000 #define KS2_MSMC_SEGMENT_TETRIS 8 #define KS2_MSMC_SEGMENT_NETCP 9 #define KS2_MSMC_SEGMENT_QM_PDSP 10 |
