diff options
author | Chander Kashyap <chander.kashyap@linaro.org> | 2011-04-14 19:05:18 +0000 |
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committer | Minkyu Kang <mk7.kang@samsung.com> | 2011-05-26 19:30:46 +0900 |
commit | b0ad8621777048c2781393a8b6a42112598218cf (patch) | |
tree | 3282f59d6f48971ce0162eacc1699f0602273c95 /arch/arm/include | |
parent | 920c428d0a871eb6fe1c127a0b01385b1c56b0c2 (diff) | |
download | blackbird-obmc-uboot-b0ad8621777048c2781393a8b6a42112598218cf.tar.gz blackbird-obmc-uboot-b0ad8621777048c2781393a8b6a42112598218cf.zip |
S5P:SROM config code moved to s5p-common directory
SROM config code is made common for S5P series of boards.
smdkc100.c now refers to s5p-common/sromc.c for SROM related
subroutines.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r-- | arch/arm/include/asm/arch-s5pc1xx/sromc.h (renamed from arch/arm/include/asm/arch-s5pc1xx/smc.h) | 8 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-s5pc2xx/sromc.h | 51 |
2 files changed, 55 insertions, 4 deletions
diff --git a/arch/arm/include/asm/arch-s5pc1xx/smc.h b/arch/arm/include/asm/arch-s5pc1xx/sromc.h index 88f4ffe33a..3800a8dbae 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/smc.h +++ b/arch/arm/include/asm/arch-s5pc1xx/sromc.h @@ -23,8 +23,8 @@ * Only SROMC is defined as of now */ -#ifndef __ASM_ARCH_SMC_H_ -#define __ASM_ARCH_SMC_H_ +#ifndef __ASM_ARCH_SROMC_H_ +#define __ASM_ARCH_SROMC_H_ #define SMC_DATA16_WIDTH(x) (1<<((x*4)+0)) #define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ @@ -41,13 +41,13 @@ #define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ #ifndef __ASSEMBLY__ -struct s5pc1xx_smc { +struct s5p_sromc { unsigned int bw; unsigned int bc[6]; }; #endif /* __ASSEMBLY__ */ /* Configure the Band Width and Bank Control Regs for required SROMC Bank */ -void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf); +void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); #endif /* __ASM_ARCH_SMC_H_ */ diff --git a/arch/arm/include/asm/arch-s5pc2xx/sromc.h b/arch/arm/include/asm/arch-s5pc2xx/sromc.h new file mode 100644 index 0000000000..f616bcb37b --- /dev/null +++ b/arch/arm/include/asm/arch-s5pc2xx/sromc.h @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2010 Samsung Electronics + * Naveen Krishna Ch <ch.naveen@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Note: This file contains the register description for SROMC + * + */ + +#ifndef __ASM_ARCH_SROMC_H_ +#define __ASM_ARCH_SROMC_H_ + +#define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0)) +#define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ + /* 1-> Byte base address*/ +#define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2)) +#define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3)) + +#define SROMC_BC_TACS(x) (x << 28) /* address set-up */ +#define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */ +#define SROMC_BC_TACC(x) (x << 16) /* access cycle */ +#define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */ +#define SROMC_BC_TAH(x) (x << 8) /* address holding time */ +#define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */ +#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ + +#ifndef __ASSEMBLY__ +struct s5p_sromc { + unsigned int bw; + unsigned int bc[4]; +}; +#endif /* __ASSEMBLY__ */ + +/* Configure the Band Width and Bank Control Regs for required SROMC Bank */ +void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); + +#endif /* __ASM_ARCH_SROMC_H_ */ |