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| author | Peng Fan <Peng.Fan@freescale.com> | 2015-10-29 15:54:44 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-11-12 17:38:09 +0100 |
| commit | 8702f5ab5da686d0bb25c0dfbf1fc46bcf402a80 (patch) | |
| tree | 87ea56a9f9eeda80a81ec64e4fa730531be1bcac /arch/arm/include/asm/imx-common | |
| parent | 04acd0e5d9ace923dec8eed00ed5878cf462be70 (diff) | |
| download | blackbird-obmc-uboot-8702f5ab5da686d0bb25c0dfbf1fc46bcf402a80.tar.gz blackbird-obmc-uboot-8702f5ab5da686d0bb25c0dfbf1fc46bcf402a80.zip | |
imx: lcdif: use one register structure for i.MXes
Share one lcdif structure for i.MXes.
1. Discard struct mxs_lcdif_regs from imx-regs.h of i.MX7
2. Add i.MX6SX/6UL/7D support in imx-lcdif.h of imx-common
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/include/asm/imx-common')
| -rw-r--r-- | arch/arm/include/asm/imx-common/regs-lcdif.h | 28 |
1 files changed, 21 insertions, 7 deletions
diff --git a/arch/arm/include/asm/imx-common/regs-lcdif.h b/arch/arm/include/asm/imx-common/regs-lcdif.h index fff6379a7e..5a4f61f77b 100644 --- a/arch/arm/include/asm/imx-common/regs-lcdif.h +++ b/arch/arm/include/asm/imx-common/regs-lcdif.h @@ -1,5 +1,5 @@ /* - * Freescale i.MX28 LCDIF Register Definitions + * Freescale i.MX28/6SX/6UL/7D LCDIF Register Definitions * * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> * on behalf of DENX Software Engineering GmbH @@ -10,8 +10,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __MX28_REGS_LCDIF_H__ -#define __MX28_REGS_LCDIF_H__ +#ifndef __IMX_REGS_LCDIF_H__ +#define __IMX_REGS_LCDIF_H__ #ifndef __ASSEMBLY__ #include <asm/imx-common/regs-common.h> @@ -19,7 +19,8 @@ struct mxs_lcdif_regs { mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */ mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */ -#if defined(CONFIG_MX28) +#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ + defined(CONFIG_MX7) mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */ #endif mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */ @@ -54,7 +55,8 @@ struct mxs_lcdif_regs { #endif mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */ mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */ -#if defined(CONFIG_MX28) +#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ + defined(CONFIG_MX7) mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ #endif mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */ @@ -62,6 +64,18 @@ struct mxs_lcdif_regs { mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */ mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */ mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */ +#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7) + mxs_reg_32(hw_lcdif_thres) + mxs_reg_32(hw_lcdif_as_ctrl) + mxs_reg_32(hw_lcdif_as_buf) + mxs_reg_32(hw_lcdif_as_next_buf) + mxs_reg_32(hw_lcdif_as_clrkeylow) + mxs_reg_32(hw_lcdif_as_clrkeyhigh) + mxs_reg_32(hw_lcdif_as_sync_delay) + mxs_reg_32(hw_lcdif_as_debug3) + mxs_reg_32(hw_lcdif_as_debug4) + mxs_reg_32(hw_lcdif_as_debug5) +#endif }; #endif @@ -194,7 +208,7 @@ struct mxs_lcdif_regs { #if defined(CONFIG_MX23) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24 -#elif defined(CONFIG_MX28) +#else #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 #endif @@ -214,4 +228,4 @@ struct mxs_lcdif_regs { #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0 -#endif /* __MX28_REGS_LCDIF_H__ */ +#endif /* __IMX_REGS_LCDIF_H__ */ |
