diff options
| author | Fabio Estevam <fabio.estevam@freescale.com> | 2012-10-15 05:37:16 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2012-10-17 18:09:34 +0200 |
| commit | 782b02884126cc258056e8bf581a410a934f7372 (patch) | |
| tree | f3abf9cfdf7cd45427aa60d4d71b79cc2c1d3995 /arch/arm/include/asm/arch-mx5 | |
| parent | 758c3449451f20402af72fa0754a1ce32ba9af48 (diff) | |
| download | blackbird-obmc-uboot-782b02884126cc258056e8bf581a410a934f7372.tar.gz blackbird-obmc-uboot-782b02884126cc258056e8bf581a410a934f7372.zip | |
mx5: lowlevel_init.S: Fix PLL settings for mx53
Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz.
Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz
instead.
Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI
at 1080p because the IPU clock cannot reach the requested frequency.
Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its
maximum frequency.
Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little
bit to allow easier comparison with the original clock setup from FSL U-boot.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/arch-mx5')
| -rw-r--r-- | arch/arm/include/asm/arch-mx5/imx-regs.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 46017f4ad0..1d060fd23e 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -308,6 +308,10 @@ #define DP_MFD_400 (3 - 1) #define DP_MFN_400 1 +#define DP_OP_455 ((9 << 4) + ((2 - 1) << 0)) +#define DP_MFD_455 (48 - 1) +#define DP_MFN_455 23 + #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) #define DP_MFD_216 (4 - 1) #define DP_MFN_216 3 |
