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| author | Tom Rini <trini@ti.com> | 2014-07-29 09:41:35 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-07-29 09:41:35 -0400 |
| commit | 362f16b1e9e94024a511adae9977d145ef942b50 (patch) | |
| tree | e0e359fb074493fa8deab65abe0feb4b8fefde3a /arch/arm/include/asm/arch-keystone/ddr3.h | |
| parent | 302e609fe653baf1ae3a7573d2f4eafd86ab696b (diff) | |
| parent | 9d195a546179bc732aba9eacccf0a9a3db591288 (diff) | |
| download | blackbird-obmc-uboot-362f16b1e9e94024a511adae9977d145ef942b50.tar.gz blackbird-obmc-uboot-362f16b1e9e94024a511adae9977d145ef942b50.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'arch/arm/include/asm/arch-keystone/ddr3.h')
| -rw-r--r-- | arch/arm/include/asm/arch-keystone/ddr3.h | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h new file mode 100644 index 0000000000..4d229a25fa --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/ddr3.h @@ -0,0 +1,56 @@ +/* + * DDR3 + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DDR3_H_ +#define _DDR3_H_ + +#include <asm/arch/hardware.h> + +struct ddr3_phy_config { + unsigned int pllcr; + unsigned int pgcr1_mask; + unsigned int pgcr1_val; + unsigned int ptr0; + unsigned int ptr1; + unsigned int ptr2; + unsigned int ptr3; + unsigned int ptr4; + unsigned int dcr_mask; + unsigned int dcr_val; + unsigned int dtpr0; + unsigned int dtpr1; + unsigned int dtpr2; + unsigned int mr0; + unsigned int mr1; + unsigned int mr2; + unsigned int dtcr; + unsigned int pgcr2; + unsigned int zq0cr1; + unsigned int zq1cr1; + unsigned int zq2cr1; + unsigned int pir_v1; + unsigned int pir_v2; +}; + +struct ddr3_emif_config { + unsigned int sdcfg; + unsigned int sdtim1; + unsigned int sdtim2; + unsigned int sdtim3; + unsigned int sdtim4; + unsigned int zqcfg; + unsigned int sdrfc; +}; + +void ddr3_init(void); +void ddr3_reset_ddrphy(void); +void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); +void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg); + +#endif |
