path: root/arch/arm/cpu
diff options
authorMingkai Hu <>2016-07-07 12:22:12 +0800
committerTom Rini <>2016-07-08 17:16:49 -0400
commitd73718f3236c520a92efa401084c658e6cc067f3 (patch)
tree012ae524657977219b686318ff399c8d6ebe85ab /arch/arm/cpu
parentd56dd0b1f8eb1dc13d4e6227a485fca5b9e94c1e (diff)
armv8: Enable CPUECTLR.SMPEN for coherency
For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is set. The SMPEN bit should be set before enabling the data cache. If not enabled, the cache is not coherent with other cores and data corruption could occur. For A57/A72, SMPEN bit enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster. This bit should be set before enabling the caches and MMU, or performing any cache and TLB maintenance operations. Signed-off-by: Mingkai Hu <> Signed-off-by: Gong Qianyu <> Reviewed-by: Masahiro Yamada <>
Diffstat (limited to 'arch/arm/cpu')
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 670e323b61..dfce469206 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -81,6 +81,14 @@ reset:
msr cpacr_el1, x0 /* Enable FP/SIMD */
+ /* Enalbe SMPEN bit for coherency.
+ * This register is not architectural but at the moment
+ * this bit should be set for A53/A57/A72.
+ */
+ mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */
+ orr x0, x0, #0x40
+ msr S3_1_c15_c2_1, x0
/* Apply ARM core specific erratas */
bl apply_core_errata
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