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authorTom Warren <twarren.nvidia@gmail.com>2012-12-11 13:34:15 +0000
committerTom Warren <twarren@nvidia.com>2013-01-16 13:40:07 -0700
commitb2871037d2c4c5f55b8de8ac593babbdab6624cb (patch)
tree6a2d7ea87099d3fd4380a30999d53fc3f79936dd /arch/arm/cpu/tegra20-common
parent5576aab5173e81462b852c35fe8d1c03c310afc2 (diff)
downloadblackbird-obmc-uboot-b2871037d2c4c5f55b8de8ac593babbdab6624cb.tar.gz
blackbird-obmc-uboot-b2871037d2c4c5f55b8de8ac593babbdab6624cb.zip
Tegra30: Add common CPU (shared) files
These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/tegra20-common')
-rw-r--r--arch/arm/cpu/tegra20-common/warmboot.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/tegra20-common/warmboot.c b/arch/arm/cpu/tegra20-common/warmboot.c
index 157b9abc45..0d472cfe33 100644
--- a/arch/arm/cpu/tegra20-common/warmboot.c
+++ b/arch/arm/cpu/tegra20-common/warmboot.c
@@ -46,7 +46,7 @@ DECLARE_GLOBAL_DATA_PTR;
* This is the place in SRAM where the SDRAM parameters are stored. There
* are 4 blocks, one for each RAM code
*/
-#define SDRAM_PARAMS_BASE (AP20_BASE_PA_SRAM + 0x188)
+#define SDRAM_PARAMS_BASE (NV_PA_BASE_SRAM + 0x188)
/* TODO: If we later add support for the Misc GP controller, refactor this */
union xm2cfga_reg {
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