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| author | Stephen Warren <swarren@nvidia.com> | 2014-03-21 12:28:51 -0600 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2014-04-17 08:41:05 -0700 |
| commit | 6ac1e542c6ff8413698e59d83ae11ab51f59e8c2 (patch) | |
| tree | 33f77b2e3ec47bbf5a6897392d483c246aa99767 /arch/arm/cpu/tegra20-common | |
| parent | dd45948dd748581dba5b666fe17601f32205cda2 (diff) | |
| download | blackbird-obmc-uboot-6ac1e542c6ff8413698e59d83ae11ab51f59e8c2.tar.gz blackbird-obmc-uboot-6ac1e542c6ff8413698e59d83ae11ab51f59e8c2.zip | |
ARM: tegra: pinctrl: make pmux_func values consistent on Tegra20
For consistency with other SoCs, modify Tegra20's enum pmux_func to:
* Remove PMUX_FUNC values that aren't real
* Use the same PMUX_FUNC_RSVD[1-4] values, and ensure (RSVD1 & 3)==0;
this will be assumed by pinmux_set_func() in a future patch.
Unfortunately, PMUX_FUNC_RSVD is still used in the pin macros. Use a
private define inside the driver to prevent this from causing compilaton
errors. This will be cleaned up when the pin tables are re-written in a
later patch in this series.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/tegra20-common')
| -rw-r--r-- | arch/arm/cpu/tegra20-common/pinmux.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/cpu/tegra20-common/pinmux.c b/arch/arm/cpu/tegra20-common/pinmux.c index 40301e13c2..14467f01f5 100644 --- a/arch/arm/cpu/tegra20-common/pinmux.c +++ b/arch/arm/cpu/tegra20-common/pinmux.c @@ -307,7 +307,9 @@ struct tegra_pingroup_desc { /* A pin group number which is not used */ #define PIN_RESERVED \ - PIN(NONE, NONE, NONE, NONE, NONE, NONE, NONE) + PIN(NONE, NONE, RSVD, RSVD, RSVD, RSVD, RSVD) + +#define PMUX_FUNC_RSVD ((enum pmux_func)-1) const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = { PIN(ATA, NAND, IDE, NAND, GMI, RSVD, IDE), |
