am33xx: Rework config_io_ctrl slightly

This function sets a number of related registers to the same value (the
registers in question all have the same field descriptions and are
related in operation).  Rather than defining a struct and setting the
value repeatedly, just pass in the value.

Signed-off-by: Tom Rini <trini@ti.com>

2 files changed, 7 insertions, 15 deletions

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 993f3da007..597d62f61b 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -120,11 +120,11 @@ void config_ddr_data(int macrono, const struct ddr_data *data)
 	writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
 }
 
-void config_io_ctrl(struct ddr_ioctrl *ioctrl)
+void config_io_ctrl(unsigned long val)
 {
-	writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl);
-	writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl);
-	writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl);
-	writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl);
-	writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl);
+	writel(val, &ioctrl_reg->cm0ioctl);
+	writel(val, &ioctrl_reg->cm1ioctl);
+	writel(val, &ioctrl_reg->cm2ioctl);
+	writel(val, &ioctrl_reg->dt0ioctl);
+	writel(val, &ioctrl_reg->dt1ioctl);
 }
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 0190ec65e7..3219045447 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -116,8 +116,6 @@ static void config_vtp(void)
 
 void config_ddr(short ddr_type)
 {
-	struct ddr_ioctrl ioctrl;
-
 	enable_emif_clocks();
 
 	if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
@@ -132,13 +130,7 @@ void config_ddr(short ddr_type)
 		writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
 		writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
 
-		ioctrl.cmd1ctl = DDR2_IOCTRL_VALUE;
-		ioctrl.cmd2ctl = DDR2_IOCTRL_VALUE;
-		ioctrl.cmd3ctl = DDR2_IOCTRL_VALUE;
-		ioctrl.data1ctl = DDR2_IOCTRL_VALUE;
-		ioctrl.data2ctl = DDR2_IOCTRL_VALUE;
-
-		config_io_ctrl(&ioctrl);
+		config_io_ctrl(DDR2_IOCTRL_VALUE);
 
 		/* Set CKE to be controlled by EMIF/DDR PHY */
 		writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);