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author | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2014-12-19 20:20:52 +0900 |
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committer | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2014-12-30 17:45:25 +0900 |
commit | b614e16cc07113dc890ecc83649b89da1bced464 (patch) | |
tree | cb5c47751c4dfb9bd886846c0ee20f7faea3c4da /arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c | |
parent | 125738e819a3b9d15210794b3dcef9f4d9bcf866 (diff) | |
download | blackbird-obmc-uboot-b614e16cc07113dc890ecc83649b89da1bced464.tar.gz blackbird-obmc-uboot-b614e16cc07113dc890ecc83649b89da1bced464.zip |
ARM: UniPhier: add DDR PHY training code
This training code provides run-time adjustment of DDR PHY parameters
for stable DDR operation.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Diffstat (limited to 'arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c')
-rw-r--r-- | arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c index 328b2f4d9a..1973ab04c2 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c @@ -7,6 +7,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/umc-regs.h> +#include <asm/arch/ddrphy-regs.h> static inline void umc_start_ssif(void __iomem *ssif_base) { @@ -94,6 +95,10 @@ static inline int umc_init_sub(int freq, int size_ch0, int size_ch1) void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); + void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); + void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1); + void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); + void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1); umc_dram_init_start(dramcont0); umc_dram_init_start(dramcont1); @@ -102,12 +107,32 @@ static inline int umc_init_sub(int freq, int size_ch0, int size_ch1) writel(0x00000101, dramcont0 + UMC_DIOCTLA); + ddrphy_init(phy0_0, freq, size_ch0); + + ddrphy_prepare_training(phy0_0, 0); + ddrphy_training(phy0_0); + writel(0x00000103, dramcont0 + UMC_DIOCTLA); + ddrphy_init(phy0_1, freq, size_ch0); + + ddrphy_prepare_training(phy0_1, 1); + ddrphy_training(phy0_1); + writel(0x00000101, dramcont1 + UMC_DIOCTLA); + ddrphy_init(phy1_0, freq, size_ch1); + + ddrphy_prepare_training(phy1_0, 0); + ddrphy_training(phy1_0); + writel(0x00000103, dramcont1 + UMC_DIOCTLA); + ddrphy_init(phy1_1, freq, size_ch1); + + ddrphy_prepare_training(phy1_1, 1); + ddrphy_training(phy1_1); + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); |