ARM: UniPhier: add UniPhier SoC support code

These are used by Panasonic UniPhier SoC family.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

12 files changed, 618 insertions, 0 deletions

diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
new file mode 100644
index 0000000000..b385e19544
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
@@ -0,0 +1,10 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
+obj-y += boot-mode.o
+obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
+		sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
+obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
+	umc_init.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c
new file mode 100644
index 0000000000..85f37f299b
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/bcu-regs.h>
+
+#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
+
+void bcu_init(void)
+{
+	int shift;
+
+	writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */
+	writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
+	writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
+	writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
+	writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
+
+	/* Specify DDR channel */
+	shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
+	writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
+
+	shift -= 32;
+	writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
+
+	shift -= 32;
+	writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c
new file mode 100644
index 0000000000..27d772e8cb
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/board.h>
+
+int checkboard(void)
+{
+	puts("Board: PH1-LD4 Board\n");
+
+	return check_support_card();
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c
new file mode 100644
index 0000000000..4302277dfc
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/led.h>
+#include <asm/arch/board.h>
+
+void bcu_init(void);
+void sbc_init(void);
+void sg_init(void);
+void pll_init(void);
+void pin_init(void);
+void clkrst_init(void);
+
+int board_postclk_init(void)
+{
+	bcu_init();
+
+	sbc_init();
+
+	sg_init();
+
+	pll_init();
+
+	uniphier_board_init();
+
+	led_write(B, 1, , );
+
+	clkrst_init();
+
+	led_write(B, 2, , );
+
+	pin_init();
+
+	led_write(B, 3, , );
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c
new file mode 100644
index 0000000000..d359b56291
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c
@@ -0,0 +1 @@
+#include "../ph1-pro4/boot-mode.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c
new file mode 100644
index 0000000000..18965a94c5
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sc-regs.h>
+
+void clkrst_init(void)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	tmp = readl(SC_RSTCTRL);
+	tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
+		| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
+	writel(tmp, SC_RSTCTRL);
+	readl(SC_RSTCTRL); /* dummy read */
+
+	/* privide clocks */
+	tmp = readl(SC_CLKCTRL);
+	tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
+	     | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
+	writel(tmp, SC_CLKCTRL);
+	readl(SC_CLKCTRL); /* dummy read */
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c
new file mode 100644
index 0000000000..a7429402f3
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sg-regs.h>
+
+void pin_init(void)
+{
+	u32 tmp;
+
+	/* Comment format:    PAD Name -> Function Name */
+
+#ifdef CONFIG_UNIPHIER_SERIAL
+	sg_set_pinsel(85, 1);	/* HSDOUT3 -> RXD0 */
+	sg_set_pinsel(88, 1);	/* HDDOUT6 -> TXD0 */
+
+	sg_set_pinsel(69, 23);	/* PCIOWR -> TXD1 */
+	sg_set_pinsel(70, 23);	/* PCIORD -> RXD1 */
+
+	sg_set_pinsel(128, 13);	/* XIRQ6 -> TXD2 */
+	sg_set_pinsel(129, 13);	/* XIRQ7 -> RXD2 */
+
+	sg_set_pinsel(110, 1);	/* SBO0 -> TXD3 */
+	sg_set_pinsel(111, 1);	/* SBI0 -> RXD3 */
+#endif
+
+#ifdef CONFIG_NAND_DENALI
+	sg_set_pinsel(158, 0);	/* XNFRE -> XNFRE_GB */
+	sg_set_pinsel(159, 0);	/* XNFWE -> XNFWE_GB */
+	sg_set_pinsel(160, 0);	/* XFALE -> NFALE_GB */
+	sg_set_pinsel(161, 0);	/* XFCLE -> NFCLE_GB */
+	sg_set_pinsel(162, 0);	/* XNFWP -> XFNWP_GB */
+	sg_set_pinsel(163, 0);	/* XNFCE0 -> XNFCE0_GB */
+	sg_set_pinsel(164, 0);	/* NANDRYBY0 -> NANDRYBY0_GB */
+	sg_set_pinsel(22, 0);	/* MMCCLK  -> XFNCE1_GB */
+	sg_set_pinsel(23, 0);	/* MMCCMD  -> NANDRYBY1_GB */
+	sg_set_pinsel(24, 0);	/* MMCDAT0 -> NFD0_GB */
+	sg_set_pinsel(25, 0);	/* MMCDAT1 -> NFD1_GB */
+	sg_set_pinsel(26, 0);	/* MMCDAT2 -> NFD2_GB */
+	sg_set_pinsel(27, 0);	/* MMCDAT3 -> NFD3_GB */
+	sg_set_pinsel(28, 0);	/* MMCDAT4 -> NFD4_GB */
+	sg_set_pinsel(29, 0);	/* MMCDAT5 -> NFD5_GB */
+	sg_set_pinsel(30, 0);	/* MMCDAT6 -> NFD6_GB */
+	sg_set_pinsel(31, 0);	/* MMCDAT7 -> NFD7_GB */
+#endif
+
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+	sg_set_pinsel(53, 0);	/* USB0VBUS -> USB0VBUS */
+	sg_set_pinsel(54, 0);	/* USB0OD   -> USB0OD */
+	sg_set_pinsel(55, 0);	/* USB1VBUS -> USB1VBUS */
+	sg_set_pinsel(56, 0);	/* USB1OD   -> USB1OD */
+	/* sg_set_pinsel(67, 23); */ /* PCOE -> USB2VBUS */
+	/* sg_set_pinsel(68, 23); */ /* PCWAIT -> USB2OD */
+#endif
+
+	tmp = readl(SG_IECTRL);
+	tmp |= 0x41;
+	writel(tmp, SG_IECTRL);
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c
new file mode 100644
index 0000000000..68b9d5ff27
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sc-regs.h>
+#include <asm/arch/sg-regs.h>
+
+#undef DPLL_SSC_RATE_1PER
+
+void dpll_init(void)
+{
+	u32 tmp;
+
+	/*
+	 * Set Frequency
+	 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
+	 * to FOUT (DPLLCTRL.bit[29:20])
+	 */
+	tmp = readl(SC_DPLLCTRL);
+	tmp &= ~0x000f0000;
+#if CONFIG_DDR_FREQ == 1600
+	tmp |= 0x000c0000;
+#elif CONFIG_DDR_FREQ == 1333
+	tmp |= 0x000d0000;
+#else
+# error "Unknown frequency"
+#endif
+
+#if defined(DPLL_SSC_RATE_1PER)
+	tmp &= ~SC_DPLLCTRL_SSC_RATE;
+#else
+	tmp |= SC_DPLLCTRL_SSC_RATE;
+#endif
+	writel(tmp, SC_DPLLCTRL);
+
+	tmp = readl(SC_DPLLCTRL2);
+	tmp |= SC_DPLLCTRL2_NRSTDS;
+	writel(tmp, SC_DPLLCTRL2);
+}
+
+void upll_init(void)
+{
+	u32 tmp, clk_mode_upll, clk_mode_axosel;
+
+	tmp = readl(SG_PINMON0);
+	clk_mode_upll   = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
+	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+	/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
+	tmp = readl(SC_UPLLCTRL);
+	tmp &= ~0x18000000;
+	writel(tmp, SC_UPLLCTRL);
+
+	if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
+		if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+		    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+			/* AXO: 25MHz */
+			tmp &= ~0x07ffffff;
+			tmp |= 0x0228f5c0;
+		} else {
+			/* AXO: default 24.576MHz */
+			tmp &= ~0x07ffffff;
+			tmp |= 0x02328000;
+		}
+	}
+
+	writel(tmp, SC_UPLLCTRL);
+
+	/* set 1 to K_LD(UPLLCTRL.bit[27]) */
+	tmp |= 0x08000000;
+	writel(tmp, SC_UPLLCTRL);
+
+	/* wait 10 usec */
+	udelay(10);
+
+	/* set 1 to SNRT(UPLLCTRL.bit[28]) */
+	tmp |= 0x10000000;
+	writel(tmp, SC_UPLLCTRL);
+}
+
+void vpll_init(void)
+{
+	u32 tmp, clk_mode_axosel;
+
+	tmp = readl(SG_PINMON0);
+	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+	/* set 1 to VPLA27WP and VPLA27WP */
+	tmp = readl(SC_VPLL27ACTRL);
+	tmp |= 0x00000001;
+	writel(tmp, SC_VPLL27ACTRL);
+	tmp = readl(SC_VPLL27BCTRL);
+	tmp |= 0x00000001;
+	writel(tmp, SC_VPLL27BCTRL);
+
+	/* Set 0 to VPLA_K_LD and VPLB_K_LD */
+	tmp = readl(SC_VPLL27ACTRL3);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27ACTRL3);
+	tmp = readl(SC_VPLL27BCTRL3);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27BCTRL3);
+
+	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
+	tmp = readl(SC_VPLL27ACTRL2);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27ACTRL2);
+	tmp = readl(SC_VPLL27BCTRL2);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27BCTRL2);
+
+	/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
+	tmp = readl(SC_VPLL27ACTRL2);
+	tmp &= ~0x0000007f;
+	tmp |= 0x00000020;
+	writel(tmp, SC_VPLL27ACTRL2);
+	tmp = readl(SC_VPLL27BCTRL2);
+	tmp &= ~0x0000007f;
+	tmp |= 0x00000020;
+	writel(tmp, SC_VPLL27BCTRL2);
+
+	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+		/* AXO: 25MHz */
+		tmp = readl(SC_VPLL27ACTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x00066664;
+		writel(tmp, SC_VPLL27ACTRL3);
+		tmp = readl(SC_VPLL27BCTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x00066664;
+		writel(tmp, SC_VPLL27BCTRL3);
+	} else {
+		/* AXO: default 24.576MHz */
+		tmp = readl(SC_VPLL27ACTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x000f5800;
+		writel(tmp, SC_VPLL27ACTRL3);
+		tmp = readl(SC_VPLL27BCTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x000f5800;
+		writel(tmp, SC_VPLL27BCTRL3);
+	}
+
+	/* Set 1 to VPLA_K_LD and VPLB_K_LD */
+	tmp = readl(SC_VPLL27ACTRL3);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27ACTRL3);
+	tmp = readl(SC_VPLL27BCTRL3);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27BCTRL3);
+
+	/* wait 10 usec */
+	udelay(10);
+
+	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
+	tmp = readl(SC_VPLL27ACTRL2);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27ACTRL2);
+	tmp = readl(SC_VPLL27BCTRL2);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27BCTRL2);
+
+	/* set 0 to VPLA27WP and VPLA27WP */
+	tmp = readl(SC_VPLL27ACTRL);
+	tmp &= ~0x00000001;
+	writel(tmp, SC_VPLL27ACTRL);
+	tmp = readl(SC_VPLL27BCTRL);
+	tmp |= ~0x00000001;
+	writel(tmp, SC_VPLL27BCTRL);
+}
+
+void pll_init(void)
+{
+	dpll_init();
+	upll_init();
+	vpll_init();
+
+	/*
+	 * Wait 500 usec until dpll get stable
+	 * We wait 10 usec in upll_init() and vpll_init()
+	 * so 20 usec can be saved here.
+	 */
+	udelay(480);
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c
new file mode 100644
index 0000000000..837b2a891b
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c
@@ -0,0 +1 @@
+#include "../ph1-pro4/pll_spectrum.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
new file mode 100644
index 0000000000..a37ed1674f
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sbc-regs.h>
+#include <asm/arch/sg-regs.h>
+
+void sbc_init(void)
+{
+	/* XECS1: sub/boot memory (boot swap = off/on) */
+	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
+	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
+	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
+	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
+
+#if !defined(CONFIG_SPL_BUILD)
+	/* XECS0: boot/sub memory (boot swap = off/on) */
+	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
+	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
+	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
+	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
+#endif
+	/* XECS3: peripherals */
+	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
+	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
+	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
+	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
+
+	/* base address regsiters */
+	writel(0x0000bc01, SBBASE0);
+	writel(0x0400bc01, SBBASE1);
+	writel(0x0800bf01, SBBASE3);
+
+#if !defined(CONFIG_SPL_BUILD)
+	/* enable access to sub memory when boot swap is on */
+	sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
+#endif
+	sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c
new file mode 100644
index 0000000000..b4dd799a88
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sg-regs.h>
+
+void sg_init(void)
+{
+	u32 tmp;
+
+	/* Set DDR size */
+	tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
+	tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
+#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
+	tmp |= SG_MEMCONF_SPARSEMEM;
+#endif
+	writel(tmp, SG_MEMCONF);
+
+	/* Input ports must be enabled deasserting reset of cores */
+	tmp = readl(SG_IECTRL);
+	tmp |= 0x1;
+	writel(tmp, SG_IECTRL);
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c
new file mode 100644
index 0000000000..1344ac1caa
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/umc-regs.h>
+
+static inline void umc_start_ssif(void __iomem *ssif_base)
+{
+	writel(0x00000000, ssif_base + 0x0000b004);
+	writel(0xffffffff, ssif_base + 0x0000c004);
+	writel(0x000fffcf, ssif_base + 0x0000c008);
+	writel(0x00000001, ssif_base + 0x0000b000);
+	writel(0x00000001, ssif_base + 0x0000c000);
+	writel(0x03010101, ssif_base + UMC_MDMCHSEL);
+	writel(0x03010100, ssif_base + UMC_DMDCHSEL);
+
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
+	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
+
+	writel(0x00000001, ssif_base + UMC_CPURST);
+	writel(0x00000001, ssif_base + UMC_IDSRST);
+	writel(0x00000001, ssif_base + UMC_IXMRST);
+	writel(0x00000001, ssif_base + UMC_MDMRST);
+	writel(0x00000001, ssif_base + UMC_MDDRST);
+	writel(0x00000001, ssif_base + UMC_SIORST);
+	writel(0x00000001, ssif_base + UMC_VIORST);
+	writel(0x00000001, ssif_base + UMC_FRCRST);
+	writel(0x00000001, ssif_base + UMC_RGLRST);
+	writel(0x00000001, ssif_base + UMC_AIORST);
+	writel(0x00000001, ssif_base + UMC_DMDRST);
+}
+
+void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
+		       int size, int freq)
+{
+	if (freq == 1333) {
+		writel(0x45990b11, dramcont + UMC_CMDCTLA);
+		writel(0x16958924, dramcont + UMC_CMDCTLB);
+		writel(0x5101046A, dramcont + UMC_INITCTLA);
+
+		if (size == 1)
+			writel(0x27028B0A, dramcont + UMC_INITCTLB);
+		else if (size == 2)
+			writel(0x38028B0A, dramcont + UMC_INITCTLB);
+
+		writel(0x000FF0FF, dramcont + UMC_INITCTLC);
+		writel(0x00000b51, dramcont + UMC_DRMMR0);
+	} else if (freq == 1600) {
+		writel(0x36BB0F17, dramcont + UMC_CMDCTLA);
+		writel(0x18C6AA24, dramcont + UMC_CMDCTLB);
+		writel(0x5101387F, dramcont + UMC_INITCTLA);
+
+		if (size == 1)
+			writel(0x2F030D3F, dramcont + UMC_INITCTLB);
+		else if (size == 2)
+			writel(0x43030D3F, dramcont + UMC_INITCTLB);
+
+		writel(0x00FF00FF, dramcont + UMC_INITCTLC);
+		writel(0x00000d71, dramcont + UMC_DRMMR0);
+	}
+
+	writel(0x00000006, dramcont + UMC_DRMMR1);
+
+	if (freq == 1333)
+		writel(0x00000290, dramcont + UMC_DRMMR2);
+	else if (freq == 1600)
+		writel(0x00000298, dramcont + UMC_DRMMR2);
+
+	writel(0x00000800, dramcont + UMC_DRMMR3);
+
+	if (freq == 1333) {
+		if (size == 1)
+			writel(0x00240512, dramcont + UMC_SPCCTLA);
+		else if (size == 2)
+			writel(0x00350512, dramcont + UMC_SPCCTLA);
+
+		writel(0x00ff0006, dramcont + UMC_SPCCTLB);
+		writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
+	} else if (freq == 1600) {
+		if (size == 1)
+			writel(0x002B0617, dramcont + UMC_SPCCTLA);
+		else if (size == 2)
+			writel(0x003F0617, dramcont + UMC_SPCCTLA);
+
+		writel(0x00ff0008, dramcont + UMC_SPCCTLB);
+		writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
+	}
+
+	writel(0x04060806, dramcont + UMC_WDATACTL_D0);
+	writel(0x04a02000, dramcont + UMC_DATASET);
+	writel(0x00000000, ca_base + 0x2300);
+	writel(0x00400020, dramcont + UMC_DCCGCTL);
+	writel(0x00000003, dramcont + 0x7000);
+	writel(0x0000000f, dramcont + 0x8000);
+	writel(0x000000c3, dramcont + 0x8004);
+	writel(0x00000071, dramcont + 0x8008);
+	writel(0x0000003b, dramcont + UMC_DICGCTLA);
+	writel(0x020a0808, dramcont + UMC_DICGCTLB);
+	writel(0x00000004, dramcont + UMC_FLOWCTLG);
+	writel(0x80000201, ca_base + 0xc20);
+	writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
+	writel(0x00200000, dramcont + UMC_FLOWCTLB);
+	writel(0x00004444, dramcont + UMC_FLOWCTLC);
+	writel(0x200a0a00, dramcont + UMC_SPCSETB);
+	writel(0x00000000, dramcont + UMC_SPCSETD);
+	writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
+}
+
+static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
+{
+	void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
+	void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
+	void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
+	void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
+	void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+
+	umc_dram_init_start(dramcont0);
+	umc_dram_init_start(dramcont1);
+	umc_dram_init_poll(dramcont0);
+	umc_dram_init_poll(dramcont1);
+
+	writel(0x00000101, dramcont0 + UMC_DIOCTLA);
+
+	writel(0x00000101, dramcont1 + UMC_DIOCTLA);
+
+	umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
+	umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
+
+	umc_start_ssif(ssif_base);
+
+	return 0;
+}
+
+int umc_init(void)
+{
+	return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
+					CONFIG_SDRAM1_SIZE / 0x08000000);
+}
+
+#if CONFIG_DDR_FREQ != 1333 && CONFIG_DDR_FREQ != 1600
+#error Unsupported DDR Frequency.
+#endif
+
+#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
+    (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
+    CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
+/* OK */
+#else
+#error Unsupported DDR configuration.
+#endif