omap4: make omap4 code common for future reuse

Much of omap4 soc support code can be reused for omap5.
Move them to the omap-common directory to facilitate
this.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

6 files changed, 0 insertions, 2717 deletions

diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index e7ee0b8c0a..d91272958f 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -25,15 +25,9 @@ include $(TOPDIR)/config.mk
 
 LIB	=  $(obj)lib$(SOC).o
 
-SOBJS	+= lowlevel_init.o
-
-COBJS	+= board.o
-COBJS	+= clocks.o
-COBJS	+= emif.o
 COBJS	+= sdram_elpida.o
 
 ifndef CONFIG_SPL_BUILD
-COBJS	+= mem.o
 COBJS	+= sys_info.o
 endif
 
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
deleted file mode 100644
index 2497e3e729..0000000000
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ /dev/null
@@ -1,384 +0,0 @@
-/*
- *
- * Common functions for OMAP4 based boards
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- *	Aneesh V	<aneesh@ti.com>
- *	Steve Sakoman	<steve@sakoman.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/armv7.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/sizes.h>
-#include <asm/arch/emif.h>
-#include <asm/arch/gpio.h>
-#include "omap4_mux_data.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
-
-static const struct gpio_bank gpio_bank_44xx[6] = {
-	{ (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
-};
-
-const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * We use static variables because global data is not ready yet.
- * Initialized data is available in SPL right from the beginning.
- * We would not typically need to save these parameters in regular
- * U-Boot. This is needed only in SPL at the moment.
- */
-u32 omap4_boot_device = BOOT_DEVICE_MMC1;
-u32 omap4_boot_mode = MMCSD_MODE_FAT;
-
-u32 omap_boot_device(void)
-{
-	return omap4_boot_device;
-}
-
-u32 omap_boot_mode(void)
-{
-	return omap4_boot_mode;
-}
-
-/*
- * Some tuning of IOs for optimal power and performance
- */
-static void do_io_settings(void)
-{
-	u32 lpddr2io;
-	struct control_lpddr2io_regs *lpddr2io_regs =
-		(struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
-	struct omap4_sys_ctrl_regs *const ctrl =
-		(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
-
-	u32 omap4_rev = omap_revision();
-
-	if (omap4_rev == OMAP4430_ES1_0)
-		lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
-	else if (omap4_rev == OMAP4430_ES2_0)
-		lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
-	else
-		lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
-
-	/* EMIF1 */
-	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
-	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
-	/* No pull for GR10 as per hw team's recommendation */
-	writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
-		&lpddr2io_regs->control_lpddr2io1_2);
-	writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3);
-
-	/* EMIF2 */
-	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
-	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
-	/* No pull for GR10 as per hw team's recommendation */
-	writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
-		&lpddr2io_regs->control_lpddr2io2_2);
-	writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3);
-
-	/*
-	 * Some of these settings (TRIM values) come from eFuse and are
-	 * in turn programmed in the eFuse at manufacturing time after
-	 * calibration of the device. Do the software over-ride only if
-	 * the device is not correctly trimmed
-	 */
-	if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) {
-
-		writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
-			&ctrl->control_ldosram_iva_voltage_ctrl);
-
-		writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
-			&ctrl->control_ldosram_mpu_voltage_ctrl);
-
-		writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
-			&ctrl->control_ldosram_core_voltage_ctrl);
-	}
-
-	if (!readl(&ctrl->control_efuse_1))
-		writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
-
-	if (!readl(&ctrl->control_efuse_2))
-		writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
-}
-#endif
-
-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
-{
-	int i;
-	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
-
-	for (i = 0; i < size; i++, pad++)
-		writew(pad->val, base + pad->offset);
-}
-
-static void set_muxconf_regs_essential(void)
-{
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
-		   sizeof(core_padconf_array_essential) /
-		   sizeof(struct pad_conf_entry));
-
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
-		   sizeof(wkup_padconf_array_essential) /
-		   sizeof(struct pad_conf_entry));
-
-	if (omap_revision() >= OMAP4460_ES1_0)
-		do_set_mux(CONTROL_PADCONF_WKUP,
-				 wkup_padconf_array_essential_4460,
-				 sizeof(wkup_padconf_array_essential_4460) /
-				 sizeof(struct pad_conf_entry));
-}
-
-static void set_mux_conf_regs(void)
-{
-	switch (omap4_hw_init_context()) {
-	case OMAP_INIT_CONTEXT_SPL:
-		set_muxconf_regs_essential();
-		break;
-	case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
-		set_muxconf_regs_non_essential();
-		break;
-	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
-	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
-		set_muxconf_regs_essential();
-		set_muxconf_regs_non_essential();
-		break;
-	}
-}
-
-static u32 cortex_a9_rev(void)
-{
-
-	unsigned int rev;
-
-	/* Read Main ID Register (MIDR) */
-	asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
-
-	return rev;
-}
-
-static void init_omap4_revision(void)
-{
-	/*
-	 * For some of the ES2/ES1 boards ID_CODE is not reliable:
-	 * Also, ES1 and ES2 have different ARM revisions
-	 * So use ARM revision for identification
-	 */
-	unsigned int arm_rev = cortex_a9_rev();
-
-	switch (arm_rev) {
-	case MIDR_CORTEX_A9_R0P1:
-		*omap4_revision = OMAP4430_ES1_0;
-		break;
-	case MIDR_CORTEX_A9_R1P2:
-		switch (readl(CONTROL_ID_CODE)) {
-		case OMAP4430_CONTROL_ID_CODE_ES2_0:
-			*omap4_revision = OMAP4430_ES2_0;
-			break;
-		case OMAP4430_CONTROL_ID_CODE_ES2_1:
-			*omap4_revision = OMAP4430_ES2_1;
-			break;
-		case OMAP4430_CONTROL_ID_CODE_ES2_2:
-			*omap4_revision = OMAP4430_ES2_2;
-			break;
-		default:
-			*omap4_revision = OMAP4430_ES2_0;
-			break;
-		}
-		break;
-	case MIDR_CORTEX_A9_R1P3:
-		*omap4_revision = OMAP4430_ES2_3;
-		break;
-	case MIDR_CORTEX_A9_R2P10:
-		switch (readl(CONTROL_ID_CODE)) {
-		case OMAP4460_CONTROL_ID_CODE_ES1_0:
-			*omap4_revision = OMAP4460_ES1_0;
-			break;
-		case OMAP4460_CONTROL_ID_CODE_ES1_1:
-			*omap4_revision = OMAP4460_ES1_1;
-			break;
-		default:
-			*omap4_revision = OMAP4460_ES1_0;
-			break;
-		}
-		break;
-	default:
-		*omap4_revision = OMAP4430_SILICON_ID_INVALID;
-		break;
-	}
-}
-
-void omap_rev_string(char *omap4_rev_string)
-{
-	u32 omap4_rev = omap_revision();
-	u32 omap4_variant = (omap4_rev & 0xFFFF0000) >> 16;
-	u32 major_rev = (omap4_rev & 0x00000F00) >> 8;
-	u32 minor_rev = (omap4_rev & 0x000000F0) >> 4;
-
-	sprintf(omap4_rev_string, "OMAP%x ES%x.%x", omap4_variant, major_rev,
-		minor_rev);
-}
-
-/*
- * Routine: s_init
- * Description: Does early system init of watchdog, muxing,  andclocks
- * Watchdog disable is done always. For the rest what gets done
- * depends on the boot mode in which this function is executed
- *   1. s_init of SPL running from SRAM
- *   2. s_init of U-Boot running from FLASH
- *   3. s_init of U-Boot loaded to SDRAM by SPL
- *   4. s_init of U-Boot loaded to SDRAM by ROM code using the
- *	Configuration Header feature
- * Please have a look at the respective functions to see what gets
- * done in each of these cases
- * This function is called with SRAM stack.
- */
-void s_init(void)
-{
-	init_omap4_revision();
-	watchdog_init();
-	set_mux_conf_regs();
-#ifdef CONFIG_SPL_BUILD
-	setup_clocks_for_console();
-	preloader_console_init();
-	do_io_settings();
-#endif
-	prcm_init();
-#ifdef CONFIG_SPL_BUILD
-	/* For regular u-boot sdram_init() is called from dram_init() */
-	sdram_init();
-#endif
-}
-
-/*
- * Routine: wait_for_command_complete
- * Description: Wait for posting to finish on watchdog
- */
-void wait_for_command_complete(struct watchdog *wd_base)
-{
-	int pending = 1;
-	do {
-		pending = readl(&wd_base->wwps);
-	} while (pending);
-}
-
-/*
- * Routine: watchdog_init
- * Description: Shut down watch dogs
- */
-void watchdog_init(void)
-{
-	struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
-
-	writel(WD_UNLOCK1, &wd2_base->wspr);
-	wait_for_command_complete(wd2_base);
-	writel(WD_UNLOCK2, &wd2_base->wspr);
-}
-
-
-/*
- * This function finds the SDRAM size available in the system
- * based on DMM section configurations
- * This is needed because the size of memory installed may be
- * different on different versions of the board
- */
-u32 omap4_sdram_size(void)
-{
-	u32 section, i, total_size = 0, size, addr;
-	for (i = 0; i < 4; i++) {
-		section	= __raw_readl(OMAP44XX_DMM_LISA_MAP_BASE + i*4);
-		addr = section & OMAP44XX_SYS_ADDR_MASK;
-		/* See if the address is valid */
-		if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
-		    (addr < OMAP44XX_DRAM_ADDR_SPACE_END)) {
-			size	= ((section & OMAP44XX_SYS_SIZE_MASK) >>
-				   OMAP44XX_SYS_SIZE_SHIFT);
-			size	= 1 << size;
-			size	*= SZ_16M;
-			total_size += size;
-		}
-	}
-	return total_size;
-}
-
-
-/*
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- */
-int dram_init(void)
-{
-	sdram_init();
-	gd->ram_size = omap4_sdram_size();
-
-	return 0;
-}
-
-/*
- * Print board information
- */
-int checkboard(void)
-{
-	puts(sysinfo.board_string);
-	return 0;
-}
-
-/*
-* This function is called by start_armboot. You can reliably use static
-* data. Any boot-time function that require static data should be
-* called from here
-*/
-int arch_cpu_init(void)
-{
-	return 0;
-}
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-void v7_outer_cache_enable(void)
-{
-	set_pl310_ctrl_reg(1);
-}
-
-void v7_outer_cache_disable(void)
-{
-	set_pl310_ctrl_reg(0);
-}
-#endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
deleted file mode 100644
index 095ba39aeb..0000000000
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ /dev/null
@@ -1,941 +0,0 @@
-/*
- *
- * Clock initialization for OMAP4
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com>
- *
- * Based on previous work by:
- *	Santosh Shilimkar <santosh.shilimkar@ti.com>
- *	Rajendra Nayak <rnayak@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/omap_common.h>
-#include <asm/gpio.h>
-#include <asm/arch/clocks.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/utils.h>
-#include <asm/omap_gpio.h>
-
-#ifndef CONFIG_SPL_BUILD
-/*
- * printing to console doesn't work unless
- * this code is executed from SPL
- */
-#define printf(fmt, args...)
-#define puts(s)
-#endif
-
-#define abs(x) (((x) < 0) ? ((x)*-1) : (x))
-
-struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
-
-static const u32 sys_clk_array[8] = {
-	12000000,	       /* 12 MHz */
-	13000000,	       /* 13 MHz */
-	16800000,	       /* 16.8 MHz */
-	19200000,	       /* 19.2 MHz */
-	26000000,	       /* 26 MHz */
-	27000000,	       /* 27 MHz */
-	38400000,	       /* 38.4 MHz */
-};
-
-/*
- * The M & N values in the following tables are created using the
- * following tool:
- * tools/omap/clocks_get_m_n.c
- * Please use this tool for creating the table for any new frequency.
- */
-
-/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */
-static const struct dpll_params mpu_dpll_params_1840mhz[NUM_SYS_CLKS] = {
-	{230, 2, 1, -1, -1, -1, -1, -1},	/* 12 MHz   */
-	{920, 12, 1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{219, 3, 1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
-	{575, 11, 1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
-	{460, 12, 1, -1, -1, -1, -1, -1},	/* 26 MHz   */
-	{920, 26, 1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{575, 23, 1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
-};
-
-/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
-static const struct dpll_params mpu_dpll_params_1584mhz[NUM_SYS_CLKS] = {
-	{66, 0, 1, -1, -1, -1, -1, -1},		/* 12 MHz   */
-	{792, 12, 1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{330, 6, 1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
-	{165, 3, 1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
-	{396, 12, 1, -1, -1, -1, -1, -1},	/* 26 MHz   */
-	{88, 2, 1, -1, -1, -1, -1, -1},		/* 27 MHz   */
-	{165, 7, 1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
-};
-
-/* dpll locked at 1200 MHz - MPU clk at 600 MHz */
-static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
-	{50, 0, 1, -1, -1, -1, -1, -1},		/* 12 MHz   */
-	{600, 12, 1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{250, 6, 1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
-	{125, 3, 1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
-	{300, 12, 1, -1, -1, -1, -1, -1},	/* 26 MHz   */
-	{200, 8, 1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{125, 7, 1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
-};
-
-static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
-	{200, 2, 1, 5, 8, 4, 6, 5},	/* 12 MHz   */
-	{800, 12, 1, 5, 8, 4, 6, 5},	/* 13 MHz   */
-	{619, 12, 1, 5, 8, 4, 6, 5},	/* 16.8 MHz */
-	{125, 2, 1, 5, 8, 4, 6, 5},	/* 19.2 MHz */
-	{400, 12, 1, 5, 8, 4, 6, 5},	/* 26 MHz   */
-	{800, 26, 1, 5, 8, 4, 6, 5},	/* 27 MHz   */
-	{125, 5, 1, 5, 8, 4, 6, 5}	/* 38.4 MHz */
-};
-
-static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
-	{127, 1, 1, 5, 8, 4, 6, 5},	/* 12 MHz   */
-	{762, 12, 1, 5, 8, 4, 6, 5},	/* 13 MHz   */
-	{635, 13, 1, 5, 8, 4, 6, 5},	/* 16.8 MHz */
-	{635, 15, 1, 5, 8, 4, 6, 5},	/* 19.2 MHz */
-	{381, 12, 1, 5, 8, 4, 6, 5},	/* 26 MHz   */
-	{254, 8, 1, 5, 8, 4, 6, 5},	/* 27 MHz   */
-	{496, 24, 1, 5, 8, 4, 6, 5}	/* 38.4 MHz */
-};
-
-static const struct dpll_params
-		core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
-	{200, 2, 2, 5, 8, 4, 6, 5},	/* 12 MHz   */
-	{800, 12, 2, 5, 8, 4, 6, 5},	/* 13 MHz   */
-	{619, 12, 2, 5, 8, 4, 6, 5},	/* 16.8 MHz */
-	{125, 2, 2, 5, 8, 4, 6, 5},	/* 19.2 MHz */
-	{400, 12, 2, 5, 8, 4, 6, 5},	/* 26 MHz   */
-	{800, 26, 2, 5, 8, 4, 6, 5},	/* 27 MHz   */
-	{125, 5, 2, 5, 8, 4, 6, 5}	/* 38.4 MHz */
-};
-
-static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
-	{64, 0, 8, 6, 12, 9, 4, 5},	/* 12 MHz   */
-	{768, 12, 8, 6, 12, 9, 4, 5},	/* 13 MHz   */
-	{320, 6, 8, 6, 12, 9, 4, 5},	/* 16.8 MHz */
-	{40, 0, 8, 6, 12, 9, 4, 5},	/* 19.2 MHz */
-	{384, 12, 8, 6, 12, 9, 4, 5},	/* 26 MHz   */
-	{256, 8, 8, 6, 12, 9, 4, 5},	/* 27 MHz   */
-	{20, 0, 8, 6, 12, 9, 4, 5}	/* 38.4 MHz */
-};
-
-static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
-	{931, 11, -1, -1, 4, 7, -1, -1},	/* 12 MHz   */
-	{931, 12, -1, -1, 4, 7, -1, -1},	/* 13 MHz   */
-	{665, 11, -1, -1, 4, 7, -1, -1},	/* 16.8 MHz */
-	{727, 14, -1, -1, 4, 7, -1, -1},	/* 19.2 MHz */
-	{931, 25, -1, -1, 4, 7, -1, -1},	/* 26 MHz   */
-	{931, 26, -1, -1, 4, 7, -1, -1},	/* 27 MHz   */
-	{412, 16, -1, -1, 4, 7, -1, -1}		/* 38.4 MHz */
-};
-
-/* ABE M & N values with sys_clk as source */
-static const struct dpll_params
-		abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
-	{49, 5, 1, 1, -1, -1, -1, -1},	/* 12 MHz   */
-	{68, 8, 1, 1, -1, -1, -1, -1},	/* 13 MHz   */
-	{35, 5, 1, 1, -1, -1, -1, -1},	/* 16.8 MHz */
-	{46, 8, 1, 1, -1, -1, -1, -1},	/* 19.2 MHz */
-	{34, 8, 1, 1, -1, -1, -1, -1},	/* 26 MHz   */
-	{29, 7, 1, 1, -1, -1, -1, -1},	/* 27 MHz   */
-	{64, 24, 1, 1, -1, -1, -1, -1}	/* 38.4 MHz */
-};
-
-/* ABE M & N values with 32K clock as source */
-static const struct dpll_params abe_dpll_params_32k_196608khz = {
-	750, 0, 1, 1, -1, -1, -1, -1
-};
-
-
-static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
-	{80, 0, 2, -1, -1, -1, -1, -1},		/* 12 MHz   */
-	{960, 12, 2, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{400, 6, 2, -1, -1, -1, -1, -1},	/* 16.8 MHz */
-	{50, 0, 2, -1, -1, -1, -1, -1},		/* 19.2 MHz */
-	{480, 12, 2, -1, -1, -1, -1, -1},	/* 26 MHz   */
-	{320, 8, 2, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{25, 0, 2, -1, -1, -1, -1, -1}		/* 38.4 MHz */
-};
-
-static inline u32 __get_sys_clk_index(void)
-{
-	u32 ind;
-	/*
-	 * For ES1 the ROM code calibration of sys clock is not reliable
-	 * due to hw issue. So, use hard-coded value. If this value is not
-	 * correct for any board over-ride this function in board file
-	 * From ES2.0 onwards you will get this information from
-	 * CM_SYS_CLKSEL
-	 */
-	if (omap_revision() == OMAP4430_ES1_0)
-		ind = OMAP_SYS_CLK_IND_38_4_MHZ;
-	else {
-		/* SYS_CLKSEL - 1 to match the dpll param array indices */
-		ind = (readl(&prcm->cm_sys_clksel) &
-			CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
-	}
-	return ind;
-}
-
-u32 get_sys_clk_index(void)
-	__attribute__ ((weak, alias("__get_sys_clk_index")));
-
-u32 get_sys_clk_freq(void)
-{
-	u8 index = get_sys_clk_index();
-	return sys_clk_array[index];
-}
-
-static inline void do_bypass_dpll(u32 *const base)
-{
-	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
-
-	clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
-			CM_CLKMODE_DPLL_DPLL_EN_MASK,
-			DPLL_EN_FAST_RELOCK_BYPASS <<
-			CM_CLKMODE_DPLL_EN_SHIFT);
-}
-
-static inline void wait_for_bypass(u32 *const base)
-{
-	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
-	if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
-				LDELAY)) {
-		printf("Bypassing DPLL failed %p\n", base);
-	}
-}
-
-static inline void do_lock_dpll(u32 *const base)
-{
-	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
-	clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
-		      CM_CLKMODE_DPLL_DPLL_EN_MASK,
-		      DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
-}
-
-static inline void wait_for_lock(u32 *const base)
-{
-	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
-	if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
-		&dpll_regs->cm_idlest_dpll, LDELAY)) {
-		printf("DPLL locking failed for %p\n", base);
-		hang();
-	}
-}
-
-static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
-				u8 lock)
-{
-	u32 temp;
-	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
-	bypass_dpll(base);
-
-	/* Set M & N */
-	temp = readl(&dpll_regs->cm_clksel_dpll);
-
-	temp &= ~CM_CLKSEL_DPLL_M_MASK;
-	temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
-
-	temp &= ~CM_CLKSEL_DPLL_N_MASK;
-	temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
-
-	writel(temp, &dpll_regs->cm_clksel_dpll);
-
-	/* Lock */
-	if (lock)
-		do_lock_dpll(base);
-
-	/* Setup post-dividers */
-	if (params->m2 >= 0)
-		writel(params->m2, &dpll_regs->cm_div_m2_dpll);
-	if (params->m3 >= 0)
-		writel(params->m3, &dpll_regs->cm_div_m3_dpll);
-	if (params->m4 >= 0)
-		writel(params->m4, &dpll_regs->cm_div_m4_dpll);
-	if (params->m5 >= 0)
-		writel(params->m5, &dpll_regs->cm_div_m5_dpll);
-	if (params->m6 >= 0)
-		writel(params->m6, &dpll_regs->cm_div_m6_dpll);
-	if (params->m7 >= 0)
-		writel(params->m7, &dpll_regs->cm_div_m7_dpll);
-
-	/* Wait till the DPLL locks */
-	if (lock)
-		wait_for_lock(base);
-}
-
-const struct dpll_params *get_core_dpll_params(void)
-{
-	u32 sysclk_ind = get_sys_clk_index();
-
-	switch (omap_revision()) {
-	case OMAP4430_ES1_0:
-		return &core_dpll_params_es1_1524mhz[sysclk_ind];
-	case OMAP4430_ES2_0:
-	case OMAP4430_SILICON_ID_INVALID:
-		 /* safest */
-		return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind];
-	default:
-		return &core_dpll_params_1600mhz[sysclk_ind];
-	}
-}
-
-u32 omap4_ddr_clk(void)
-{
-	u32 ddr_clk, sys_clk_khz;
-	const struct dpll_params *core_dpll_params;
-
-	sys_clk_khz = get_sys_clk_freq() / 1000;
-
-	core_dpll_params = get_core_dpll_params();
-
-	debug("sys_clk %d\n ", sys_clk_khz * 1000);
-
-	/* Find Core DPLL locked frequency first */
-	ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
-			(core_dpll_params->n + 1);
-	/*
-	 * DDR frequency is PHY_ROOT_CLK/2
-	 * PHY_ROOT_CLK = Fdpll/2/M2
-	 */
-	ddr_clk = ddr_clk / 4 / core_dpll_params->m2;
-
-	ddr_clk *= 1000;	/* convert to Hz */
-	debug("ddr_clk %d\n ", ddr_clk);
-
-	return ddr_clk;
-}
-
-/*
- * Lock MPU dpll
- *
- * Resulting MPU frequencies:
- * 4430 ES1.0	: 600 MHz
- * 4430 ES2.x	: 792 MHz (OPP Turbo)
- * 4460		: 920 MHz (OPP Turbo) - DCC disabled
- */
-void configure_mpu_dpll(void)
-{
-	const struct dpll_params *params;
-	struct dpll_regs *mpu_dpll_regs;
-	u32 omap4_rev, sysclk_ind;
-
-	omap4_rev = omap_revision();
-	sysclk_ind = get_sys_clk_index();
-
-	if (omap4_rev == OMAP4430_ES1_0)
-		params = &mpu_dpll_params_1200mhz[sysclk_ind];
-	else if (omap4_rev < OMAP4460_ES1_0)
-		params = &mpu_dpll_params_1584mhz[sysclk_ind];
-	else
-		params = &mpu_dpll_params_1840mhz[sysclk_ind];
-
-	/* DCC and clock divider settings for 4460 */
-	if (omap4_rev >= OMAP4460_ES1_0) {
-		mpu_dpll_regs =
-			(struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
-		bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
-		clrbits_le32(&prcm->cm_mpu_mpu_clkctrl,
-			MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
-		setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
-			MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
-		clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
-			CM_CLKSEL_DCC_EN_MASK);
-	}
-
-	do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK);
-	debug("MPU DPLL locked\n");
-}
-
-static void setup_dplls(void)
-{
-	u32 sysclk_ind, temp;
-	const struct dpll_params *params;
-	debug("setup_dplls\n");
-
-	sysclk_ind = get_sys_clk_index();
-
-	/* CORE dpll */
-	params = get_core_dpll_params();	/* default - safest */
-	/*
-	 * Do not lock the core DPLL now. Just set it up.
-	 * Core DPLL will be locked after setting up EMIF
-	 * using the FREQ_UPDATE method(freq_update_core())
-	 */
-	do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK);
-	/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
-	temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
-	    (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
-	    (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
-	writel(temp, &prcm->cm_clksel_core);
-	debug("Core DPLL configured\n");
-
-	/* lock PER dpll */
-	do_setup_dpll(&prcm->cm_clkmode_dpll_per,
-			&per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK);
-	debug("PER DPLL locked\n");
-
-	/* MPU dpll */
-	configure_mpu_dpll();
-}
-
-static void setup_non_essential_dplls(void)
-{
-	u32 sys_clk_khz, abe_ref_clk;
-	u32 sysclk_ind, sd_div, num, den;
-	const struct dpll_params *params;
-
-	sysclk_ind = get_sys_clk_index();
-	sys_clk_khz = get_sys_clk_freq() / 1000;
-
-	/* IVA */
-	clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
-		CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
-
-	do_setup_dpll(&prcm->cm_clkmode_dpll_iva,
-			&iva_dpll_params_1862mhz[sysclk_ind], DPLL_LOCK);
-
-	/*
-	 * USB:
-	 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
-	 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
-	 *      - where CLKINP is sys_clk in MHz
-	 * Use CLKINP in KHz and adjust the denominator accordingly so
-	 * that we have enough accuracy and at the same time no overflow
-	 */
-	params = &usb_dpll_params_1920mhz[sysclk_ind];
-	num = params->m * sys_clk_khz;
-	den = (params->n + 1) * 250 * 1000;
-	num += den - 1;
-	sd_div = num / den;
-	clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
-			CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
-			sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
-
-	/* Now setup the dpll with the regular function */
-	do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK);
-
-#ifdef CONFIG_SYS_OMAP4_ABE_SYSCK
-	params = &abe_dpll_params_sysclk_196608khz[sysclk_ind];
-	abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
-#else
-	params = &abe_dpll_params_32k_196608khz;
-	abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
-	/*
-	 * We need to enable some additional options to achieve
-	 * 196.608MHz from 32768 Hz
-	 */
-	setbits_le32(&prcm->cm_clkmode_dpll_abe,
-			CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
-			CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
-			CM_CLKMODE_DPLL_LPMODE_EN_MASK|
-			CM_CLKMODE_DPLL_REGM4XEN_MASK);
-	/* Spend 4 REFCLK cycles at each stage */
-	clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
-			CM_CLKMODE_DPLL_RAMP_RATE_MASK,
-			1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
-#endif
-
-	/* Select the right reference clk */
-	clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
-			CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
-			abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
-	/* Lock the dpll */
-	do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK);
-}
-
-static void do_scale_tps62361(u32 reg, u32 volt_mv)
-{
-	u32 temp, step;
-
-	step = volt_mv - TPS62361_BASE_VOLT_MV;
-	step /= 10;
-
-	/*
-	 * Select SET1 in TPS62361:
-	 * VSEL1 is grounded on board. So the following selects
-	 * VSEL1 = 0 and VSEL0 = 1
-	 */
-	gpio_direction_output(TPS62361_VSEL0_GPIO, 0);
-	gpio_set_value(TPS62361_VSEL0_GPIO, 1);
-
-	temp = TPS62361_I2C_SLAVE_ADDR |
-	    (reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
-	    (step << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
-	    PRM_VC_VAL_BYPASS_VALID_BIT;
-	debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
-
-	writel(temp, &prcm->prm_vc_val_bypass);
-	if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
-				&prcm->prm_vc_val_bypass, LDELAY)) {
-		puts("Scaling voltage failed for vdd_mpu from TPS\n");
-	}
-}
-
-static void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
-{
-	u32 temp, offset_code;
-	u32 step = 12660; /* 12.66 mV represented in uV */
-	u32 offset = volt_mv;
-
-	/* convert to uV for better accuracy in the calculations */
-	offset *= 1000;
-
-	if (omap_revision() == OMAP4430_ES1_0)
-		offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
-	else
-		offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
-
-	offset_code = (offset + step - 1) / step;
-	/* The code starts at 1 not 0 */
-	offset_code++;
-
-	debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
-		offset_code);
-
-	temp = SMPS_I2C_SLAVE_ADDR |
-	    (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
-	    (offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
-	    PRM_VC_VAL_BYPASS_VALID_BIT;
-	writel(temp, &prcm->prm_vc_val_bypass);
-	if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
-				&prcm->prm_vc_val_bypass, LDELAY)) {
-		printf("Scaling voltage failed for 0x%x\n", vcore_reg);
-	}
-}
-
-/*
- * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
- * We set the maximum voltages allowed here because Smart-Reflex is not
- * enabled in bootloader. Voltage initialization in the kernel will set
- * these to the nominal values after enabling Smart-Reflex
- */
-static void scale_vcores(void)
-{
-	u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp, omap4_rev;
-
-	sys_clk_khz = get_sys_clk_freq() / 1000;
-
-	/*
-	 * Setup the dedicated I2C controller for Voltage Control
-	 * I2C clk - high period 40% low period 60%
-	 */
-	cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
-	cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
-	/* values to be set in register - less by 5 & 7 respectively */
-	cycles_hi -= 5;
-	cycles_low -= 7;
-	temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
-	       (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
-	writel(temp, &prcm->prm_vc_cfg_i2c_clk);
-
-	/* Disable high speed mode and all advanced features */
-	writel(0x0, &prcm->prm_vc_cfg_i2c_mode);
-
-	omap4_rev = omap_revision();
-	/* TPS - supplies vdd_mpu on 4460 */
-	if (omap4_rev >= OMAP4460_ES1_0) {
-		volt = 1430;
-		do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
-	}
-
-	/*
-	 * VCORE 1
-	 *
-	 * 4430 : supplies vdd_mpu
-	 * Setting a high voltage for Nitro mode as smart reflex is not enabled.
-	 * We use the maximum possible value in the AVS range because the next
-	 * higher voltage in the discrete range (code >= 0b111010) is way too
-	 * high
-	 *
-	 * 4460 : supplies vdd_core
-	 */
-	if (omap4_rev < OMAP4460_ES1_0) {
-		volt = 1417;
-		do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
-	} else {
-		volt = 1200;
-		do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
-	}
-
-	/* VCORE 2 - supplies vdd_iva */
-	volt = 1200;
-	do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
-
-	/*
-	 * VCORE 3
-	 * 4430 : supplies vdd_core
-	 * 4460 : not connected
-	 */
-	if (omap4_rev < OMAP4460_ES1_0) {
-		volt = 1200;
-		do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
-	}
-}
-
-static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
-{
-	clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
-			enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
-	debug("Enable clock domain - %p\n", clkctrl_reg);
-}
-
-static inline void wait_for_clk_enable(u32 *clkctrl_addr)
-{
-	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
-	u32 bound = LDELAY;
-
-	while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
-		(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
-
-		clkctrl = readl(clkctrl_addr);
-		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
-			 MODULE_CLKCTRL_IDLEST_SHIFT;
-		if (--bound == 0) {
-			printf("Clock enable failed for 0x%p idlest 0x%x\n",
-				clkctrl_addr, clkctrl);
-			return;
-		}
-	}
-}
-
-static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
-				u32 wait_for_enable)
-{
-	clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
-			enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
-	debug("Enable clock module - %p\n", clkctrl_addr);
-	if (wait_for_enable)
-		wait_for_clk_enable(clkctrl_addr);
-}
-
-/*
- * Enable essential clock domains, modules and
- * do some additional special settings needed
- */
-static void enable_basic_clocks(void)
-{
-	u32 i, max = 100, wait_for_enable = 1;
-	u32 *const clk_domains_essential[] = {
-		&prcm->cm_l4per_clkstctrl,
-		&prcm->cm_l3init_clkstctrl,
-		&prcm->cm_memif_clkstctrl,
-		&prcm->cm_l4cfg_clkstctrl,
-		0
-	};
-
-	u32 *const clk_modules_hw_auto_essential[] = {
-		&prcm->cm_wkup_gpio1_clkctrl,
-		&prcm->cm_l4per_gpio2_clkctrl,
-		&prcm->cm_l4per_gpio3_clkctrl,
-		&prcm->cm_l4per_gpio4_clkctrl,
-		&prcm->cm_l4per_gpio5_clkctrl,
-		&prcm->cm_l4per_gpio6_clkctrl,
-		&prcm->cm_memif_emif_1_clkctrl,
-		&prcm->cm_memif_emif_2_clkctrl,
-		&prcm->cm_l3init_hsusbotg_clkctrl,
-		&prcm->cm_l3init_usbphy_clkctrl,
-		&prcm->cm_l4cfg_l4_cfg_clkctrl,
-		0
-	};
-
-	u32 *const clk_modules_explicit_en_essential[] = {
-		&prcm->cm_l4per_gptimer2_clkctrl,
-		&prcm->cm_l3init_hsmmc1_clkctrl,
-		&prcm->cm_l3init_hsmmc2_clkctrl,
-		&prcm->cm_l4per_mcspi1_clkctrl,
-		&prcm->cm_wkup_gptimer1_clkctrl,
-		&prcm->cm_l4per_i2c1_clkctrl,
-		&prcm->cm_l4per_i2c2_clkctrl,
-		&prcm->cm_l4per_i2c3_clkctrl,
-		&prcm->cm_l4per_i2c4_clkctrl,
-		&prcm->cm_wkup_wdtimer2_clkctrl,
-		&prcm->cm_l4per_uart3_clkctrl,
-		0
-	};
-
-	/* Enable optional additional functional clock for GPIO4 */
-	setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
-			GPIO4_CLKCTRL_OPTFCLKEN_MASK);
-
-	/* Enable 96 MHz clock for MMC1 & MMC2 */
-	setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
-			HSMMC_CLKCTRL_CLKSEL_MASK);
-	setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
-			HSMMC_CLKCTRL_CLKSEL_MASK);
-
-	/* Select 32KHz clock as the source of GPTIMER1 */
-	setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
-			GPTIMER1_CLKCTRL_CLKSEL_MASK);
-
-	/* Enable optional 48M functional clock for USB  PHY */
-	setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
-			USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
-
-	/* Put the clock domains in SW_WKUP mode */
-	for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
-		enable_clock_domain(clk_domains_essential[i],
-				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
-	}
-
-	/* Clock modules that need to be put in HW_AUTO */
-	for (i = 0; (i < max) && clk_modules_hw_auto_essential[i]; i++) {
-		enable_clock_module(clk_modules_hw_auto_essential[i],
-				    MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
-				    wait_for_enable);
-	};
-
-	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
-	for (i = 0; (i < max) && clk_modules_explicit_en_essential[i]; i++) {
-		enable_clock_module(clk_modules_explicit_en_essential[i],
-				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
-				    wait_for_enable);
-	};
-
-	/* Put the clock domains in HW_AUTO mode now */
-	for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
-		enable_clock_domain(clk_domains_essential[i],
-				    CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
-	}
-}
-
-/*
- * Enable non-essential clock domains, modules and
- * do some additional special settings needed
- */
-static void enable_non_essential_clocks(void)
-{
-	u32 i, max = 100, wait_for_enable = 0;
-	u32 *const clk_domains_non_essential[] = {
-		&prcm->cm_mpu_m3_clkstctrl,
-		&prcm->cm_ivahd_clkstctrl,
-		&prcm->cm_dsp_clkstctrl,
-		&prcm->cm_dss_clkstctrl,
-		&prcm->cm_sgx_clkstctrl,
-		&prcm->cm1_abe_clkstctrl,
-		&prcm->cm_c2c_clkstctrl,
-		&prcm->cm_cam_clkstctrl,
-		&prcm->cm_dss_clkstctrl,
-		&prcm->cm_sdma_clkstctrl,
-		0
-	};
-
-	u32 *const clk_modules_hw_auto_non_essential[] = {
-		&prcm->cm_mpu_m3_mpu_m3_clkctrl,
-		&prcm->cm_ivahd_ivahd_clkctrl,
-		&prcm->cm_ivahd_sl2_clkctrl,
-		&prcm->cm_dsp_dsp_clkctrl,
-		&prcm->cm_l3_2_gpmc_clkctrl,
-		&prcm->cm_l3instr_l3_3_clkctrl,
-		&prcm->cm_l3instr_l3_instr_clkctrl,
-		&prcm->cm_l3instr_intrconn_wp1_clkctrl,
-		&prcm->cm_l3init_hsi_clkctrl,
-		&prcm->cm_l3init_hsusbtll_clkctrl,
-		0
-	};
-
-	u32 *const clk_modules_explicit_en_non_essential[] = {
-		&prcm->cm1_abe_aess_clkctrl,
-		&prcm->cm1_abe_pdm_clkctrl,
-		&prcm->cm1_abe_dmic_clkctrl,
-		&prcm->cm1_abe_mcasp_clkctrl,
-		&prcm->cm1_abe_mcbsp1_clkctrl,
-		&prcm->cm1_abe_mcbsp2_clkctrl,
-		&prcm->cm1_abe_mcbsp3_clkctrl,
-		&prcm->cm1_abe_slimbus_clkctrl,
-		&prcm->cm1_abe_timer5_clkctrl,
-		&prcm->cm1_abe_timer6_clkctrl,
-		&prcm->cm1_abe_timer7_clkctrl,
-		&prcm->cm1_abe_timer8_clkctrl,
-		&prcm->cm1_abe_wdt3_clkctrl,
-		&prcm->cm_l4per_gptimer9_clkctrl,
-		&prcm->cm_l4per_gptimer10_clkctrl,
-		&prcm->cm_l4per_gptimer11_clkctrl,
-		&prcm->cm_l4per_gptimer3_clkctrl,
-		&prcm->cm_l4per_gptimer4_clkctrl,
-		&prcm->cm_l4per_hdq1w_clkctrl,
-		&prcm->cm_l4per_mcbsp4_clkctrl,
-		&prcm->cm_l4per_mcspi2_clkctrl,
-		&prcm->cm_l4per_mcspi3_clkctrl,
-		&prcm->cm_l4per_mcspi4_clkctrl,
-		&prcm->cm_l4per_mmcsd3_clkctrl,
-		&prcm->cm_l4per_mmcsd4_clkctrl,
-		&prcm->cm_l4per_mmcsd5_clkctrl,
-		&prcm->cm_l4per_uart1_clkctrl,
-		&prcm->cm_l4per_uart2_clkctrl,
-		&prcm->cm_l4per_uart4_clkctrl,
-		&prcm->cm_wkup_keyboard_clkctrl,
-		&prcm->cm_wkup_wdtimer2_clkctrl,
-		&prcm->cm_cam_iss_clkctrl,
-		&prcm->cm_cam_fdif_clkctrl,
-		&prcm->cm_dss_dss_clkctrl,
-		&prcm->cm_sgx_sgx_clkctrl,
-		&prcm->cm_l3init_hsusbhost_clkctrl,
-		&prcm->cm_l3init_fsusb_clkctrl,
-		0
-	};
-
-	/* Enable optional functional clock for ISS */
-	setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
-
-	/* Enable all optional functional clocks of DSS */
-	setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
-
-
-	/* Put the clock domains in SW_WKUP mode */
-	for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
-		enable_clock_domain(clk_domains_non_essential[i],
-				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
-	}
-
-	/* Clock modules that need to be put in HW_AUTO */
-	for (i = 0; (i < max) && clk_modules_hw_auto_non_essential[i]; i++) {
-		enable_clock_module(clk_modules_hw_auto_non_essential[i],
-				    MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
-				    wait_for_enable);
-	};
-
-	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
-	for (i = 0; (i < max) && clk_modules_explicit_en_non_essential[i];
-	     i++) {
-		enable_clock_module(clk_modules_explicit_en_non_essential[i],
-				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
-				    wait_for_enable);
-	};
-
-	/* Put the clock domains in HW_AUTO mode now */
-	for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
-		enable_clock_domain(clk_domains_non_essential[i],
-				    CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
-	}
-
-	/* Put camera module in no sleep mode */
-	clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
-			CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
-			MODULE_CLKCTRL_MODULEMODE_SHIFT);
-}
-
-
-void freq_update_core(void)
-{
-	u32 freq_config1 = 0;
-	const struct dpll_params *core_dpll_params;
-
-	core_dpll_params = get_core_dpll_params();
-	/* Put EMIF clock domain in sw wakeup mode */
-	enable_clock_domain(&prcm->cm_memif_clkstctrl,
-				CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
-	wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
-	wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
-
-	freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
-	    SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
-
-	freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
-				SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
-
-	freq_config1 |= (core_dpll_params->m2 <<
-			SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
-			SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
-
-	writel(freq_config1, &prcm->cm_shadow_freq_config1);
-	if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
-				&prcm->cm_shadow_freq_config1, LDELAY)) {
-		puts("FREQ UPDATE procedure failed!!");
-		hang();
-	}
-
-	/* Put EMIF clock domain back in hw auto mode */
-	enable_clock_domain(&prcm->cm_memif_clkstctrl,
-				CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
-	wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
-	wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
-}
-
-void bypass_dpll(u32 *const base)
-{
-	do_bypass_dpll(base);
-	wait_for_bypass(base);
-}
-
-void lock_dpll(u32 *const base)
-{
-	do_lock_dpll(base);
-	wait_for_lock(base);
-}
-
-void setup_clocks_for_console(void)
-{
-	/* Do not add any spl_debug prints in this function */
-	clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
-			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
-			CD_CLKCTRL_CLKTRCTRL_SHIFT);
-
-	/* Enable all UARTs - console will be on one of them */
-	clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl,
-			MODULE_CLKCTRL_MODULEMODE_MASK,
-			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
-			MODULE_CLKCTRL_MODULEMODE_SHIFT);
-
-	clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl,
-			MODULE_CLKCTRL_MODULEMODE_MASK,
-			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
-			MODULE_CLKCTRL_MODULEMODE_SHIFT);
-
-	clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
-			MODULE_CLKCTRL_MODULEMODE_MASK,
-			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
-			MODULE_CLKCTRL_MODULEMODE_SHIFT);
-
-	clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
-			MODULE_CLKCTRL_MODULEMODE_MASK,
-			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
-			MODULE_CLKCTRL_MODULEMODE_SHIFT);
-
-	clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
-			CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
-			CD_CLKCTRL_CLKTRCTRL_SHIFT);
-}
-
-void prcm_init(void)
-{
-	switch (omap4_hw_init_context()) {
-	case OMAP_INIT_CONTEXT_SPL:
-	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
-	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
-		enable_basic_clocks();
-		scale_vcores();
-		setup_dplls();
-		setup_non_essential_dplls();
-		enable_non_essential_clocks();
-		break;
-	default:
-		break;
-	}
-}
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
deleted file mode 100644
index 988b2050fa..0000000000
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ /dev/null
@@ -1,1254 +0,0 @@
-/*
- * EMIF programming
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/emif.h>
-#include <asm/arch/clocks.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/omap_common.h>
-#include <asm/utils.h>
-
-static inline u32 emif_num(u32 base)
-{
-	if (base == OMAP44XX_EMIF1)
-		return 1;
-	else if (base == OMAP44XX_EMIF2)
-		return 2;
-	else
-		return 0;
-}
-
-static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
-{
-	u32 mr;
-	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
-	mr_addr |= cs << OMAP44XX_REG_CS_SHIFT;
-	writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
-	if (omap_revision() == OMAP4430_ES2_0)
-		mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
-	else
-		mr = readl(&emif->emif_lpddr2_mode_reg_data);
-	debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
-	      cs, mr_addr, mr);
-	return mr;
-}
-
-static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
-{
-	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
-	mr_addr |= cs << OMAP44XX_REG_CS_SHIFT;
-	writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
-	writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
-}
-
-void emif_reset_phy(u32 base)
-{
-	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-	u32 iodft;
-
-	iodft = readl(&emif->emif_iodft_tlgc);
-	iodft |= OMAP44XX_REG_RESET_PHY_MASK;
-	writel(iodft, &emif->emif_iodft_tlgc);
-}
-
-static void do_lpddr2_init(u32 base, u32 cs)
-{
-	u32 mr_addr;
-
-	/* Wait till device auto initialization is complete */
-	while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
-		;
-	set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
-	/*
-	 * tZQINIT = 1 us
-	 * Enough loops assuming a maximum of 2GHz
-	 */
-	sdelay(2000);
-	set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
-	set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
-	/*
-	 * Enable refresh along with writing MR2
-	 * Encoding of RL in MR2 is (RL - 2)
-	 */
-	mr_addr = LPDDR2_MR2 | OMAP44XX_REG_REFRESH_EN_MASK;
-	set_mr(base, cs, mr_addr, RL_FINAL - 2);
-}
-
-static void lpddr2_init(u32 base, const struct emif_regs *regs)
-{
-	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
-	/* Not NVM */
-	clrbits_le32(&emif->emif_lpddr2_nvm_config, OMAP44XX_REG_CS1NVMEN_MASK);
-
-	/*
-	 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
-	 * when EMIF_SDRAM_CONFIG register is written
-	 */
-	setbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK);
-
-	/*
-	 * Set the SDRAM_CONFIG and PHY_CTRL for the
-	 * un-locked frequency & default RL
-	 */
-	writel(regs->sdram_config_init, &emif->emif_sdram_config);
-	writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
-
-	do_lpddr2_init(base, CS0);
-	if (regs->sdram_config & OMAP44XX_REG_EBANK_MASK)
-		do_lpddr2_init(base, CS1);
-
-	writel(regs->sdram_config, &emif->emif_sdram_config);
-	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
-
-	/* Enable refresh now */
-	clrbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK);
-
-}
-
-static void emif_update_timings(u32 base, const struct emif_regs *regs)
-{
-	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
-	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
-	writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
-	writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
-	writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
-	if (omap_revision() == OMAP4430_ES1_0) {
-		/* ES1 bug EMIF should be in force idle during freq_update */
-		writel(0, &emif->emif_pwr_mgmt_ctrl);
-	} else {
-		writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
-		writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
-	}
-	writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
-	writel(regs->zq_config, &emif->emif_zq_config);
-	writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
-	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
-
-	if (omap_revision() >= OMAP4460_ES1_0) {
-		writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
-			&emif->emif_l3_config);
-	} else {
-		writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
-			&emif->emif_l3_config);
-	}
-}
-
-#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
-
-static u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM;
-static u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN;
-static u32 *const emif_sizes = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_SIZE;
-
-/*
- * Organization and refresh requirements for LPDDR2 devices of different
- * types and densities. Derived from JESD209-2 section 2.4
- */
-const struct lpddr2_addressing addressing_table[] = {
-	/* Banks tREFIx10     rowx32,rowx16      colx32,colx16	density */
-	{BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
-	{BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
-	{BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
-	{BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
-	{BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
-	{BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
-	{BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
-	{BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
-	{BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
-	{BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
-};
-
-static const u32 lpddr2_density_2_size_in_mbytes[] = {
-	8,			/* 64Mb */
-	16,			/* 128Mb */
-	32,			/* 256Mb */
-	64,			/* 512Mb */
-	128,			/* 1Gb   */
-	256,			/* 2Gb   */
-	512,			/* 4Gb   */
-	1024,			/* 8Gb   */
-	2048,			/* 16Gb  */
-	4096			/* 32Gb  */
-};
-
-/*
- * Calculate the period of DDR clock from frequency value and set the
- * denominator and numerator in global variables for easy access later
- */
-static void set_ddr_clk_period(u32 freq)
-{
-	/*
-	 * period = 1/freq
-	 * period_in_ns = 10^9/freq
-	 */
-	*T_num = 1000000000;
-	*T_den = freq;
-	cancel_out(T_num, T_den, 200);
-
-}
-
-/*
- * Convert time in nano seconds to number of cycles of DDR clock
- */
-static inline u32 ns_2_cycles(u32 ns)
-{
-	return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
-}
-
-/*
- * ns_2_cycles with the difference that the time passed is 2 times the actual
- * value(to avoid fractions). The cycles returned is for the original value of
- * the timing parameter
- */
-static inline u32 ns_x2_2_cycles(u32 ns)
-{
-	return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
-}
-
-/*
- * Find addressing table index based on the device's type(S2 or S4) and
- * density
- */
-s8 addressing_table_index(u8 type, u8 density, u8 width)
-{
-	u8 index;
-	if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
-		return -1;
-
-	/*
-	 * Look at the way ADDR_TABLE_INDEX* values have been defined
-	 * in emif.h compared to LPDDR2_DENSITY_* values
-	 * The table is layed out in the increasing order of density
-	 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
-	 * at the end
-	 */
-	if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
-		index = ADDR_TABLE_INDEX1GS2;
-	else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
-		index = ADDR_TABLE_INDEX2GS2;
-	else
-		index = density;
-
-	debug("emif: addressing table index %d\n", index);
-
-	return index;
-}
-
-/*
- * Find the the right timing table from the array of timing
- * tables of the device using DDR clock frequency
- */
-static const struct lpddr2_ac_timings *get_timings_table(const struct
-			lpddr2_ac_timings const *const *device_timings,
-			u32 freq)
-{
-	u32 i, temp, freq_nearest;
-	const struct lpddr2_ac_timings *timings = 0;
-
-	emif_assert(freq <= MAX_LPDDR2_FREQ);
-	emif_assert(device_timings);
-
-	/*
-	 * Start with the maximum allowed frequency - that is always safe
-	 */
-	freq_nearest = MAX_LPDDR2_FREQ;
-	/*
-	 * Find the timings table that has the max frequency value:
-	 *   i.  Above or equal to the DDR frequency - safe
-	 *   ii. The lowest that satisfies condition (i) - optimal
-	 */
-	for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
-		temp = device_timings[i]->max_freq;
-		if ((temp >= freq) && (temp <= freq_nearest)) {
-			freq_nearest = temp;
-			timings = device_timings[i];
-		}
-	}
-	debug("emif: timings table: %d\n", freq_nearest);
-	return timings;
-}
-
-/*
- * Finds the value of emif_sdram_config_reg
- * All parameters are programmed based on the device on CS0.
- * If there is a device on CS1, it will be same as that on CS0 or
- * it will be NVM. We don't support NVM yet.
- * If cs1_device pointer is NULL it is assumed that there is no device
- * on CS1
- */
-static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
-				const struct lpddr2_device_details *cs1_device,
-				const struct lpddr2_addressing *addressing,
-				u8 RL)
-{
-	u32 config_reg = 0;
-
-	config_reg |=  (cs0_device->type + 4) << OMAP44XX_REG_SDRAM_TYPE_SHIFT;
-	config_reg |=  EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
-			OMAP44XX_REG_IBANK_POS_SHIFT;
-
-	config_reg |= cs0_device->io_width << OMAP44XX_REG_NARROW_MODE_SHIFT;
-
-	config_reg |= RL << OMAP44XX_REG_CL_SHIFT;
-
-	config_reg |= addressing->row_sz[cs0_device->io_width] <<
-			OMAP44XX_REG_ROWSIZE_SHIFT;
-
-	config_reg |= addressing->num_banks << OMAP44XX_REG_IBANK_SHIFT;
-
-	config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
-			OMAP44XX_REG_EBANK_SHIFT;
-
-	config_reg |= addressing->col_sz[cs0_device->io_width] <<
-			OMAP44XX_REG_PAGESIZE_SHIFT;
-
-	return config_reg;
-}
-
-static u32 get_sdram_ref_ctrl(u32 freq,
-			      const struct lpddr2_addressing *addressing)
-{
-	u32 ref_ctrl = 0, val = 0, freq_khz;
-	freq_khz = freq / 1000;
-	/*
-	 * refresh rate to be set is 'tREFI * freq in MHz
-	 * division by 10000 to account for khz and x10 in t_REFI_us_x10
-	 */
-	val = addressing->t_REFI_us_x10 * freq_khz / 10000;
-	ref_ctrl |= val << OMAP44XX_REG_REFRESH_RATE_SHIFT;
-
-	return ref_ctrl;
-}
-
-static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
-			       const struct lpddr2_min_tck *min_tck,
-			       const struct lpddr2_addressing *addressing)
-{
-	u32 tim1 = 0, val = 0;
-	val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
-	tim1 |= val << OMAP44XX_REG_T_WTR_SHIFT;
-
-	if (addressing->num_banks == BANKS8)
-		val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
-							(4 * (*T_num)) - 1;
-	else
-		val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
-
-	tim1 |= val << OMAP44XX_REG_T_RRD_SHIFT;
-
-	val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
-	tim1 |= val << OMAP44XX_REG_T_RC_SHIFT;
-
-	val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
-	tim1 |= val << OMAP44XX_REG_T_RAS_SHIFT;
-
-	val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
-	tim1 |= val << OMAP44XX_REG_T_WR_SHIFT;
-
-	val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
-	tim1 |= val << OMAP44XX_REG_T_RCD_SHIFT;
-
-	val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
-	tim1 |= val << OMAP44XX_REG_T_RP_SHIFT;
-
-	return tim1;
-}
-
-static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
-			       const struct lpddr2_min_tck *min_tck)
-{
-	u32 tim2 = 0, val = 0;
-	val = max(min_tck->tCKE, timings->tCKE) - 1;
-	tim2 |= val << OMAP44XX_REG_T_CKE_SHIFT;
-
-	val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
-	tim2 |= val << OMAP44XX_REG_T_RTP_SHIFT;
-
-	/*
-	 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
-	 * same value
-	 */
-	val = ns_2_cycles(timings->tXSR) - 1;
-	tim2 |= val << OMAP44XX_REG_T_XSRD_SHIFT;
-	tim2 |= val << OMAP44XX_REG_T_XSNR_SHIFT;
-
-	val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
-	tim2 |= val << OMAP44XX_REG_T_XP_SHIFT;
-
-	return tim2;
-}
-
-static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
-			       const struct lpddr2_min_tck *min_tck,
-			       const struct lpddr2_addressing *addressing)
-{
-	u32 tim3 = 0, val = 0;
-	val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
-	tim3 |= val << OMAP44XX_REG_T_RAS_MAX_SHIFT;
-
-	val = ns_2_cycles(timings->tRFCab) - 1;
-	tim3 |= val << OMAP44XX_REG_T_RFC_SHIFT;
-
-	val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
-	tim3 |= val << OMAP44XX_REG_T_TDQSCKMAX_SHIFT;
-
-	val = ns_2_cycles(timings->tZQCS) - 1;
-	tim3 |= val << OMAP44XX_REG_ZQ_ZQCS_SHIFT;
-
-	val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
-	tim3 |= val << OMAP44XX_REG_T_CKESR_SHIFT;
-
-	return tim3;
-}
-
-static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
-			     const struct lpddr2_addressing *addressing,
-			     u8 volt_ramp)
-{
-	u32 zq = 0, val = 0;
-	if (volt_ramp)
-		val =
-		    EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
-		    addressing->t_REFI_us_x10;
-	else
-		val =
-		    EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
-		    addressing->t_REFI_us_x10;
-	zq |= val << OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT;
-
-	zq |= (REG_ZQ_ZQCL_MULT - 1) << OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT;
-
-	zq |= (REG_ZQ_ZQINIT_MULT - 1) << OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT;
-
-	zq |= REG_ZQ_SFEXITEN_ENABLE << OMAP44XX_REG_ZQ_SFEXITEN_SHIFT;
-
-	/*
-	 * Assuming that two chipselects have a single calibration resistor
-	 * If there are indeed two calibration resistors, then this flag should
-	 * be enabled to take advantage of dual calibration feature.
-	 * This data should ideally come from board files. But considering
-	 * that none of the boards today have calibration resistors per CS,
-	 * it would be an unnecessary overhead.
-	 */
-	zq |= REG_ZQ_DUALCALEN_DISABLE << OMAP44XX_REG_ZQ_DUALCALEN_SHIFT;
-
-	zq |= REG_ZQ_CS0EN_ENABLE << OMAP44XX_REG_ZQ_CS0EN_SHIFT;
-
-	zq |= (cs1_device ? 1 : 0) << OMAP44XX_REG_ZQ_CS1EN_SHIFT;
-
-	return zq;
-}
-
-static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
-				 const struct lpddr2_addressing *addressing,
-				 u8 is_derated)
-{
-	u32 alert = 0, interval;
-	interval =
-	    TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
-	if (is_derated)
-		interval *= 4;
-	alert |= interval << OMAP44XX_REG_TA_REFINTERVAL_SHIFT;
-
-	alert |= TEMP_ALERT_CONFIG_DEVCT_1 << OMAP44XX_REG_TA_DEVCNT_SHIFT;
-
-	alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << OMAP44XX_REG_TA_DEVWDT_SHIFT;
-
-	alert |= 1 << OMAP44XX_REG_TA_SFEXITEN_SHIFT;
-
-	alert |= 1 << OMAP44XX_REG_TA_CS0EN_SHIFT;
-
-	alert |= (cs1_device ? 1 : 0) << OMAP44XX_REG_TA_CS1EN_SHIFT;
-
-	return alert;
-}
-
-static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
-{
-	u32 idle = 0, val = 0;
-	if (volt_ramp)
-		val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
-	else
-		/*Maximum value in normal conditions - suggested by hw team */
-		val = 0x1FF;
-	idle |= val << OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT;
-
-	idle |= EMIF_REG_READ_IDLE_LEN_VAL << OMAP44XX_REG_READ_IDLE_LEN_SHIFT;
-
-	return idle;
-}
-
-static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
-{
-	u32 phy = 0, val = 0;
-
-	phy |= (RL + 2) << OMAP44XX_REG_READ_LATENCY_SHIFT;
-
-	if (freq <= 100000000)
-		val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
-	else if (freq <= 200000000)
-		val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
-	else
-		val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
-	phy |= val << OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
-
-	/* Other fields are constant magic values. Hardcode them together */
-	phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
-		OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
-
-	return phy;
-}
-
-static u32 get_emif_mem_size(struct emif_device_details *devices)
-{
-	u32 size_mbytes = 0, temp;
-
-	if (!devices)
-		return 0;
-
-	if (devices->cs0_device_details) {
-		temp = devices->cs0_device_details->density;
-		size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
-	}
-
-	if (devices->cs1_device_details) {
-		temp = devices->cs1_device_details->density;
-		size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
-	}
-	/* convert to bytes */
-	return size_mbytes << 20;
-}
-
-/* Gets the encoding corresponding to a given DMM section size */
-u32 get_dmm_section_size_map(u32 section_size)
-{
-	/*
-	 * Section size mapping:
-	 * 0x0: 16-MiB section
-	 * 0x1: 32-MiB section
-	 * 0x2: 64-MiB section
-	 * 0x3: 128-MiB section
-	 * 0x4: 256-MiB section
-	 * 0x5: 512-MiB section
-	 * 0x6: 1-GiB section
-	 * 0x7: 2-GiB section
-	 */
-	section_size >>= 24; /* divide by 16 MB */
-	return log_2_n_round_down(section_size);
-}
-
-static void emif_calculate_regs(
-		const struct emif_device_details *emif_dev_details,
-		u32 freq, struct emif_regs *regs)
-{
-	u32 temp, sys_freq;
-	const struct lpddr2_addressing *addressing;
-	const struct lpddr2_ac_timings *timings;
-	const struct lpddr2_min_tck *min_tck;
-	const struct lpddr2_device_details *cs0_dev_details =
-					emif_dev_details->cs0_device_details;
-	const struct lpddr2_device_details *cs1_dev_details =
-					emif_dev_details->cs1_device_details;
-	const struct lpddr2_device_timings *cs0_dev_timings =
-					emif_dev_details->cs0_device_timings;
-
-	emif_assert(emif_dev_details);
-	emif_assert(regs);
-	/*
-	 * You can not have a device on CS1 without one on CS0
-	 * So configuring EMIF without a device on CS0 doesn't
-	 * make sense
-	 */
-	emif_assert(cs0_dev_details);
-	emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
-	/*
-	 * If there is a device on CS1 it should be same type as CS0
-	 * (or NVM. But NVM is not supported in this driver yet)
-	 */
-	emif_assert((cs1_dev_details == NULL) ||
-		    (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
-		    (cs0_dev_details->type == cs1_dev_details->type));
-	emif_assert(freq <= MAX_LPDDR2_FREQ);
-
-	set_ddr_clk_period(freq);
-
-	/*
-	 * The device on CS0 is used for all timing calculations
-	 * There is only one set of registers for timings per EMIF. So, if the
-	 * second CS(CS1) has a device, it should have the same timings as the
-	 * device on CS0
-	 */
-	timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
-	emif_assert(timings);
-	min_tck = cs0_dev_timings->min_tck;
-
-	temp = addressing_table_index(cs0_dev_details->type,
-				      cs0_dev_details->density,
-				      cs0_dev_details->io_width);
-
-	emif_assert((temp >= 0));
-	addressing = &(addressing_table[temp]);
-	emif_assert(addressing);
-
-	sys_freq = get_sys_clk_freq();
-
-	regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
-							cs1_dev_details,
-							addressing, RL_BOOT);
-
-	regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
-						cs1_dev_details,
-						addressing, RL_FINAL);
-
-	regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
-
-	regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
-
-	regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
-
-	regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
-
-	regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
-
-	regs->temp_alert_config =
-	    get_temp_alert_config(cs1_dev_details, addressing, 0);
-
-	regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
-					    LPDDR2_VOLTAGE_STABLE);
-
-	regs->emif_ddr_phy_ctlr_1_init =
-			get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
-
-	regs->emif_ddr_phy_ctlr_1 =
-			get_ddr_phy_ctrl_1(freq, RL_FINAL);
-
-	regs->freq = freq;
-
-	print_timing_reg(regs->sdram_config_init);
-	print_timing_reg(regs->sdram_config);
-	print_timing_reg(regs->ref_ctrl);
-	print_timing_reg(regs->sdram_tim1);
-	print_timing_reg(regs->sdram_tim2);
-	print_timing_reg(regs->sdram_tim3);
-	print_timing_reg(regs->read_idle_ctrl);
-	print_timing_reg(regs->temp_alert_config);
-	print_timing_reg(regs->zq_config);
-	print_timing_reg(regs->emif_ddr_phy_ctlr_1);
-	print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
-}
-#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
-
-#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-/* Base AC Timing values specified by JESD209-2 for 400MHz operation */
-static const struct lpddr2_ac_timings timings_jedec_400_mhz = {
-	.max_freq = 400000000,
-	.RL = 6,
-	.tRPab = 21,
-	.tRCD = 18,
-	.tWR = 15,
-	.tRASmin = 42,
-	.tRRD = 10,
-	.tWTRx2 = 15,
-	.tXSR = 140,
-	.tXPx2 = 15,
-	.tRFCab = 130,
-	.tRTPx2 = 15,
-	.tCKE = 3,
-	.tCKESR = 15,
-	.tZQCS = 90,
-	.tZQCL = 360,
-	.tZQINIT = 1000,
-	.tDQSCKMAXx2 = 11,
-	.tRASmax = 70,
-	.tFAW = 50
-};
-
-/* Base AC Timing values specified by JESD209-2 for 333 MHz operation */
-static const struct lpddr2_ac_timings timings_jedec_333_mhz = {
-	.max_freq = 333000000,
-	.RL = 5,
-	.tRPab = 21,
-	.tRCD = 18,
-	.tWR = 15,
-	.tRASmin = 42,
-	.tRRD = 10,
-	.tWTRx2 = 15,
-	.tXSR = 140,
-	.tXPx2 = 15,
-	.tRFCab = 130,
-	.tRTPx2 = 15,
-	.tCKE = 3,
-	.tCKESR = 15,
-	.tZQCS = 90,
-	.tZQCL = 360,
-	.tZQINIT = 1000,
-	.tDQSCKMAXx2 = 11,
-	.tRASmax = 70,
-	.tFAW = 50
-};
-
-/* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
-static const struct lpddr2_ac_timings timings_jedec_200_mhz = {
-	.max_freq = 200000000,
-	.RL = 3,
-	.tRPab = 21,
-	.tRCD = 18,
-	.tWR = 15,
-	.tRASmin = 42,
-	.tRRD = 10,
-	.tWTRx2 = 20,
-	.tXSR = 140,
-	.tXPx2 = 15,
-	.tRFCab = 130,
-	.tRTPx2 = 15,
-	.tCKE = 3,
-	.tCKESR = 15,
-	.tZQCS = 90,
-	.tZQCL = 360,
-	.tZQINIT = 1000,
-	.tDQSCKMAXx2 = 11,
-	.tRASmax = 70,
-	.tFAW = 50
-};
-
-/*
- * Min tCK values specified by JESD209-2
- * Min tCK specifies the minimum duration of some AC timing parameters in terms
- * of the number of cycles. If the calculated number of cycles based on the
- * absolute time value is less than the min tCK value, min tCK value should
- * be used instead. This typically happens at low frequencies.
- */
-static const struct lpddr2_min_tck min_tck_jedec = {
-	.tRL = 3,
-	.tRP_AB = 3,
-	.tRCD = 3,
-	.tWR = 3,
-	.tRAS_MIN = 3,
-	.tRRD = 2,
-	.tWTR = 2,
-	.tXP = 2,
-	.tRTP = 2,
-	.tCKE = 3,
-	.tCKESR = 3,
-	.tFAW = 8
-};
-
-static const struct lpddr2_ac_timings const*
-			jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
-	&timings_jedec_200_mhz,
-	&timings_jedec_333_mhz,
-	&timings_jedec_400_mhz
-};
-
-static const struct lpddr2_device_timings jedec_default_timings = {
-	.ac_timings = jedec_ac_timings,
-	.min_tck = &min_tck_jedec
-};
-
-void emif_get_device_timings(u32 emif_nr,
-		const struct lpddr2_device_timings **cs0_device_timings,
-		const struct lpddr2_device_timings **cs1_device_timings)
-{
-	/* Assume Identical devices on EMIF1 & EMIF2 */
-	*cs0_device_timings = &jedec_default_timings;
-	*cs1_device_timings = &jedec_default_timings;
-}
-#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
-
-#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
-const char *get_lpddr2_type(u8 type_id)
-{
-	switch (type_id) {
-	case LPDDR2_TYPE_S4:
-		return "LPDDR2-S4";
-	case LPDDR2_TYPE_S2:
-		return "LPDDR2-S2";
-	default:
-		return NULL;
-	}
-}
-
-const char *get_lpddr2_io_width(u8 width_id)
-{
-	switch (width_id) {
-	case LPDDR2_IO_WIDTH_8:
-		return "x8";
-	case LPDDR2_IO_WIDTH_16:
-		return "x16";
-	case LPDDR2_IO_WIDTH_32:
-		return "x32";
-	default:
-		return NULL;
-	}
-}
-
-const char *get_lpddr2_manufacturer(u32 manufacturer)
-{
-	switch (manufacturer) {
-	case LPDDR2_MANUFACTURER_SAMSUNG:
-		return "Samsung";
-	case LPDDR2_MANUFACTURER_QIMONDA:
-		return "Qimonda";
-	case LPDDR2_MANUFACTURER_ELPIDA:
-		return "Elpida";
-	case LPDDR2_MANUFACTURER_ETRON:
-		return "Etron";
-	case LPDDR2_MANUFACTURER_NANYA:
-		return "Nanya";
-	case LPDDR2_MANUFACTURER_HYNIX:
-		return "Hynix";
-	case LPDDR2_MANUFACTURER_MOSEL:
-		return "Mosel";
-	case LPDDR2_MANUFACTURER_WINBOND:
-		return "Winbond";
-	case LPDDR2_MANUFACTURER_ESMT:
-		return "ESMT";
-	case LPDDR2_MANUFACTURER_SPANSION:
-		return "Spansion";
-	case LPDDR2_MANUFACTURER_SST:
-		return "SST";
-	case LPDDR2_MANUFACTURER_ZMOS:
-		return "ZMOS";
-	case LPDDR2_MANUFACTURER_INTEL:
-		return "Intel";
-	case LPDDR2_MANUFACTURER_NUMONYX:
-		return "Numonyx";
-	case LPDDR2_MANUFACTURER_MICRON:
-		return "Micron";
-	default:
-		return NULL;
-	}
-}
-
-static void display_sdram_details(u32 emif_nr, u32 cs,
-				  struct lpddr2_device_details *device)
-{
-	const char *mfg_str;
-	const char *type_str;
-	char density_str[10];
-	u32 density;
-
-	debug("EMIF%d CS%d\t", emif_nr, cs);
-
-	if (!device) {
-		debug("None\n");
-		return;
-	}
-
-	mfg_str = get_lpddr2_manufacturer(device->manufacturer);
-	type_str = get_lpddr2_type(device->type);
-
-	density = lpddr2_density_2_size_in_mbytes[device->density];
-	if ((density / 1024 * 1024) == density) {
-		density /= 1024;
-		sprintf(density_str, "%d GB", density);
-	} else
-		sprintf(density_str, "%d MB", density);
-	if (mfg_str && type_str)
-		debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
-}
-
-static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
-				  struct lpddr2_device_details *lpddr2_device)
-{
-	u32 mr = 0, temp;
-
-	mr = get_mr(base, cs, LPDDR2_MR0);
-	if (mr > 0xFF) {
-		/* Mode register value bigger than 8 bit */
-		return 0;
-	}
-
-	temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
-	if (temp) {
-		/* Not SDRAM */
-		return 0;
-	}
-	temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
-
-	if (temp) {
-		/* DNV supported - But DNV is only supported for NVM */
-		return 0;
-	}
-
-	mr = get_mr(base, cs, LPDDR2_MR4);
-	if (mr > 0xFF) {
-		/* Mode register value bigger than 8 bit */
-		return 0;
-	}
-
-	mr = get_mr(base, cs, LPDDR2_MR5);
-	if (mr >= 0xFF) {
-		/* Mode register value bigger than 8 bit */
-		return 0;
-	}
-
-	if (!get_lpddr2_manufacturer(mr)) {
-		/* Manufacturer not identified */
-		return 0;
-	}
-	lpddr2_device->manufacturer = mr;
-
-	mr = get_mr(base, cs, LPDDR2_MR6);
-	if (mr >= 0xFF) {
-		/* Mode register value bigger than 8 bit */
-		return 0;
-	}
-
-	mr = get_mr(base, cs, LPDDR2_MR7);
-	if (mr >= 0xFF) {
-		/* Mode register value bigger than 8 bit */
-		return 0;
-	}
-
-	mr = get_mr(base, cs, LPDDR2_MR8);
-	if (mr >= 0xFF) {
-		/* Mode register value bigger than 8 bit */
-		return 0;
-	}
-
-	temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
-	if (!get_lpddr2_type(temp)) {
-		/* Not SDRAM */
-		return 0;
-	}
-	lpddr2_device->type = temp;
-
-	temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
-	if (temp > LPDDR2_DENSITY_32Gb) {
-		/* Density not supported */
-		return 0;
-	}
-	lpddr2_device->density = temp;
-
-	temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
-	if (!get_lpddr2_io_width(temp)) {
-		/* IO width unsupported value */
-		return 0;
-	}
-	lpddr2_device->io_width = temp;
-
-	/*
-	 * If all the above tests pass we should
-	 * have a device on this chip-select
-	 */
-	return 1;
-}
-
-struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
-			struct lpddr2_device_details *lpddr2_dev_details)
-{
-	u32 phy;
-	u32 base = (emif_nr == 1) ? OMAP44XX_EMIF1 : OMAP44XX_EMIF2;
-	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
-	if (!lpddr2_dev_details)
-		return NULL;
-
-	/* Do the minimum init for mode register accesses */
-	if (!running_from_sdram()) {
-		phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
-		writel(phy, &emif->emif_ddr_phy_ctrl_1);
-	}
-
-	if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
-		return NULL;
-
-	display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
-
-	return lpddr2_dev_details;
-}
-#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
-
-static void do_sdram_init(u32 base)
-{
-	const struct emif_regs *regs;
-	u32 in_sdram, emif_nr;
-
-	debug(">>do_sdram_init() %x\n", base);
-
-	in_sdram = running_from_sdram();
-	emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2;
-
-#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-	emif_get_reg_dump(emif_nr, &regs);
-	if (!regs) {
-		debug("EMIF: reg dump not provided\n");
-		return;
-	}
-#else
-	/*
-	 * The user has not provided the register values. We need to
-	 * calculate it based on the timings and the DDR frequency
-	 */
-	struct emif_device_details dev_details;
-	struct emif_regs calculated_regs;
-
-	/*
-	 * Get device details:
-	 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
-	 * - Obtained from user otherwise
-	 */
-	struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
-	emif_reset_phy(base);
-	dev_details.cs0_device_details = emif_get_device_details(base, CS0,
-						&cs0_dev_details);
-	dev_details.cs1_device_details = emif_get_device_details(base, CS1,
-						&cs1_dev_details);
-	emif_reset_phy(base);
-
-	/* Return if no devices on this EMIF */
-	if (!dev_details.cs0_device_details &&
-	    !dev_details.cs1_device_details) {
-		emif_sizes[emif_nr - 1] = 0;
-		return;
-	}
-
-	if (!in_sdram)
-		emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details);
-
-	/*
-	 * Get device timings:
-	 * - Default timings specified by JESD209-2 if
-	 *   CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
-	 * - Obtained from user otherwise
-	 */
-	emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
-				&dev_details.cs1_device_timings);
-
-	/* Calculate the register values */
-	emif_calculate_regs(&dev_details, omap4_ddr_clk(), &calculated_regs);
-	regs = &calculated_regs;
-#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
-
-	/*
-	 * Initializing the LPDDR2 device can not happen from SDRAM.
-	 * Changing the timing registers in EMIF can happen(going from one
-	 * OPP to another)
-	 */
-	if (!in_sdram)
-		lpddr2_init(base, regs);
-
-	/* Write to the shadow registers */
-	emif_update_timings(base, regs);
-
-	debug("<<do_sdram_init() %x\n", base);
-}
-
-static void emif_post_init_config(u32 base)
-{
-	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-	u32 omap4_rev = omap_revision();
-
-	/* reset phy on ES2.0 */
-	if (omap4_rev == OMAP4430_ES2_0)
-		emif_reset_phy(base);
-
-	/* Put EMIF back in smart idle on ES1.0 */
-	if (omap4_rev == OMAP4430_ES1_0)
-		writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
-}
-
-static void dmm_init(u32 base)
-{
-	const struct dmm_lisa_map_regs *lisa_map_regs;
-
-#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-	emif_get_dmm_regs(&lisa_map_regs);
-#else
-	u32 emif1_size, emif2_size, mapped_size, section_map = 0;
-	u32 section_cnt, sys_addr;
-	struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
-
-	mapped_size = 0;
-	section_cnt = 3;
-	sys_addr = CONFIG_SYS_SDRAM_BASE;
-	emif1_size = emif_sizes[0];
-	emif2_size = emif_sizes[1];
-	debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
-
-	if (!emif1_size && !emif2_size)
-		return;
-
-	/* symmetric interleaved section */
-	if (emif1_size && emif2_size) {
-		mapped_size = min(emif1_size, emif2_size);
-		section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
-		section_map |= 0 << OMAP44XX_SDRC_ADDR_SHIFT;
-		/* only MSB */
-		section_map |= (sys_addr >> 24) <<
-				OMAP44XX_SYS_ADDR_SHIFT;
-		section_map |= get_dmm_section_size_map(mapped_size * 2)
-				<< OMAP44XX_SYS_SIZE_SHIFT;
-		lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
-		emif1_size -= mapped_size;
-		emif2_size -= mapped_size;
-		sys_addr += (mapped_size * 2);
-		section_cnt--;
-	}
-
-	/*
-	 * Single EMIF section(we can have a maximum of 1 single EMIF
-	 * section- either EMIF1 or EMIF2 or none, but not both)
-	 */
-	if (emif1_size) {
-		section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
-		section_map |= get_dmm_section_size_map(emif1_size)
-				<< OMAP44XX_SYS_SIZE_SHIFT;
-		/* only MSB */
-		section_map |= (mapped_size >> 24) <<
-				OMAP44XX_SDRC_ADDR_SHIFT;
-		/* only MSB */
-		section_map |= (sys_addr >> 24) << OMAP44XX_SYS_ADDR_SHIFT;
-		section_cnt--;
-	}
-	if (emif2_size) {
-		section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
-		section_map |= get_dmm_section_size_map(emif2_size) <<
-				OMAP44XX_SYS_SIZE_SHIFT;
-		/* only MSB */
-		section_map |= mapped_size >> 24 << OMAP44XX_SDRC_ADDR_SHIFT;
-		/* only MSB */
-		section_map |= sys_addr >> 24 << OMAP44XX_SYS_ADDR_SHIFT;
-		section_cnt--;
-	}
-
-	if (section_cnt == 2) {
-		/* Only 1 section - either symmetric or single EMIF */
-		lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
-		lis_map_regs_calculated.dmm_lisa_map_2 = 0;
-		lis_map_regs_calculated.dmm_lisa_map_1 = 0;
-	} else {
-		/* 2 sections - 1 symmetric, 1 single EMIF */
-		lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
-		lis_map_regs_calculated.dmm_lisa_map_1 = 0;
-	}
-
-	/* TRAP for invalid TILER mappings in section 0 */
-	lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
-
-	lisa_map_regs = &lis_map_regs_calculated;
-#endif
-	struct dmm_lisa_map_regs *hw_lisa_map_regs =
-	    (struct dmm_lisa_map_regs *)base;
-
-	writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
-	writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
-	writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
-	writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
-
-	writel(lisa_map_regs->dmm_lisa_map_3,
-		&hw_lisa_map_regs->dmm_lisa_map_3);
-	writel(lisa_map_regs->dmm_lisa_map_2,
-		&hw_lisa_map_regs->dmm_lisa_map_2);
-	writel(lisa_map_regs->dmm_lisa_map_1,
-		&hw_lisa_map_regs->dmm_lisa_map_1);
-	writel(lisa_map_regs->dmm_lisa_map_0,
-		&hw_lisa_map_regs->dmm_lisa_map_0);
-
-	if (omap_revision() >= OMAP4460_ES1_0) {
-		hw_lisa_map_regs =
-		    (struct dmm_lisa_map_regs *)OMAP44XX_MA_LISA_MAP_BASE;
-
-		writel(lisa_map_regs->dmm_lisa_map_3,
-			&hw_lisa_map_regs->dmm_lisa_map_3);
-		writel(lisa_map_regs->dmm_lisa_map_2,
-			&hw_lisa_map_regs->dmm_lisa_map_2);
-		writel(lisa_map_regs->dmm_lisa_map_1,
-			&hw_lisa_map_regs->dmm_lisa_map_1);
-		writel(lisa_map_regs->dmm_lisa_map_0,
-			&hw_lisa_map_regs->dmm_lisa_map_0);
-	}
-}
-
-/*
- * SDRAM initialization:
- * SDRAM initialization has two parts:
- * 1. Configuring the SDRAM device
- * 2. Update the AC timings related parameters in the EMIF module
- * (1) should be done only once and should not be done while we are
- * running from SDRAM.
- * (2) can and should be done more than once if OPP changes.
- * Particularly, this may be needed when we boot without SPL and
- * and using Configuration Header(CH). ROM code supports only at 50% OPP
- * at boot (low power boot). So u-boot has to switch to OPP100 and update
- * the frequency. So,
- * Doing (1) and (2) makes sense - first time initialization
- * Doing (2) and not (1) makes sense - OPP change (when using CH)
- * Doing (1) and not (2) doen't make sense
- * See do_sdram_init() for the details
- */
-void sdram_init(void)
-{
-	u32 in_sdram, size_prog, size_detect;
-
-	debug(">>sdram_init()\n");
-
-	if (omap4_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
-		return;
-
-	in_sdram = running_from_sdram();
-	debug("in_sdram = %d\n", in_sdram);
-
-	if (!in_sdram) {
-		bypass_dpll(&prcm->cm_clkmode_dpll_core);
-	}
-
-	do_sdram_init(OMAP44XX_EMIF1);
-	do_sdram_init(OMAP44XX_EMIF2);
-
-	if (!in_sdram) {
-		dmm_init(OMAP44XX_DMM_LISA_MAP_BASE);
-		emif_post_init_config(OMAP44XX_EMIF1);
-		emif_post_init_config(OMAP44XX_EMIF2);
-
-	}
-
-	/* for the shadow registers to take effect */
-	freq_update_core();
-
-	/* Do some testing after the init */
-	if (!in_sdram) {
-		size_prog = omap4_sdram_size();
-		size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
-						size_prog);
-		/* Compare with the size programmed */
-		if (size_detect != size_prog) {
-			printf("SDRAM: identified size not same as expected"
-				" size identified: %x expected: %x\n",
-				size_detect,
-				size_prog);
-		} else
-			debug("get_ram_size() successful");
-	}
-
-	debug("<<sdram_init()\n");
-}
diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
deleted file mode 100644
index 91525ecd46..0000000000
--- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- *	Aneesh V	<aneesh@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/omap4.h>
-#ifdef CONFIG_SPL_BUILD
-.global save_boot_params
-save_boot_params:
-	/*
-	 * See if the rom code passed pointer is valid:
-	 * It is not valid if it is not in non-secure SRAM
-	 * This may happen if you are booting with the help of
-	 * debugger
-	 */
-	ldr     r2, =NON_SECURE_SRAM_START
-	cmp	r2, r0
-	bgt	1f
-	ldr	r2, =NON_SECURE_SRAM_END
-	cmp	r2, r0
-	blt	1f
-
-	/* Store the boot device in omap4_boot_device */
-	ldr     r2, [r0, #BOOT_DEVICE_OFFSET]	@ r1 <- value of boot device
-	and	r2, #BOOT_DEVICE_MASK
-	ldr	r3, =omap4_boot_device
-	str     r2, [r3]			@ omap4_boot_device <- r1
-
-	/* Store the boot mode (raw/FAT) in omap4_boot_mode */
-	ldr	r2, [r0, #DEV_DESC_PTR_OFFSET]	@ get the device descriptor ptr
-	ldr	r2, [r2, #DEV_DATA_PTR_OFFSET]	@ get the pDeviceData ptr
-	ldr	r2, [r2, #BOOT_MODE_OFFSET]	@ get the boot mode
-	ldr	r3, =omap4_boot_mode
-	str	r2, [r3]
-1:
-	bx	lr
-#endif
-
-.globl lowlevel_init
-lowlevel_init:
-	/*
-	 * Setup a temporary stack
-	 */
-	ldr	sp, =LOW_LEVEL_SRAM_STACK
-
-	/*
-	 * Save the old lr(passed in ip) and the current lr to stack
-	 */
-	push	{ip, lr}
-
-	/*
-	 * go setup pll, mux, memory
-	 */
-	bl	s_init
-	pop	{ip, pc}
-
-.globl set_pl310_ctrl_reg
-set_pl310_ctrl_reg:
-	PUSH	{r4-r11, lr}	@ save registers - ROM code may pollute
-				@ our registers
-	LDR	r12, =0x102	@ Set PL310 control register - value in R0
-	.word	0xe1600070	@ SMC #0 - hand assembled because -march=armv5
-				@ call ROM Code API to set control register
-	POP	{r4-r11, pc}
diff --git a/arch/arm/cpu/armv7/omap4/mem.c b/arch/arm/cpu/armv7/omap4/mem.c
deleted file mode 100644
index 878f0e3042..0000000000
--- a/arch/arm/cpu/armv7/omap4/mem.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Steve Sakoman <steve@sakoman.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/cpu.h>
-#include <asm/arch/sys_proto.h>
-
-struct gpmc *gpmc_cfg;
-
-/*****************************************************
- * gpmc_init(): init gpmc bus
- * This code can only be executed from SRAM or SDRAM.
- *****************************************************/
-void gpmc_init(void)
-{
-	gpmc_cfg = (struct gpmc *)GPMC_BASE;
-
-	/* global settings */
-	writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
-	writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
-
-	/*
-	 * Disable the GPMC0 config set by ROM code
-	 * It conflicts with our MPDB (both at 0x08000000)
-	 */
-	writel(0, &gpmc_cfg->cs[0].config7);
-}