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| author | Wang Huan <b18965@freescale.com> | 2014-09-05 13:52:34 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-09-08 10:30:32 -0700 |
| commit | d60a2099a20254b33a314895a4b5e6a21aebd135 (patch) | |
| tree | 2fb79855edd6466a89c84cc4ce6210802aa75d06 /arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h | |
| parent | d6c1ffc7d23f4fe4ae8c91101861055b8e1501b6 (diff) | |
| download | blackbird-obmc-uboot-d60a2099a20254b33a314895a4b5e6a21aebd135.tar.gz blackbird-obmc-uboot-d60a2099a20254b33a314895a4b5e6a21aebd135.zip | |
arm: ls102xa: Add Freescale LS102xA SoC support
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h')
| -rw-r--r-- | arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h new file mode 100644 index 0000000000..834aa532bf --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h @@ -0,0 +1,12 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_LS1_SERDES_H +#define __FSL_LS1_SERDES_H + +int is_serdes_prtcl_valid(int serdes, u32 prtcl); +int serdes_lane_enabled(int lane); +#endif /* __FSL_LS1_SERDES_H */ |
