diff options
| author | Hao Zhang <hzhang@ti.com> | 2014-07-09 19:48:41 +0300 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-07-25 16:26:09 -0400 |
| commit | 101eec50f021a354487a511dc1f72691404b2b48 (patch) | |
| tree | 3ce38417d6fa5b3131307167e075c18b8f47aa41 /arch/arm/cpu/armv7/keystone/ddr3.c | |
| parent | 0b868589563ab96384b9a817bc5b82d93c573ea5 (diff) | |
| download | blackbird-obmc-uboot-101eec50f021a354487a511dc1f72691404b2b48.tar.gz blackbird-obmc-uboot-101eec50f021a354487a511dc1f72691404b2b48.zip | |
keystone2: ddr: add DDR3 PHY configs updated for PG 2.0
Add DDR3 PHY configs updated for PG 2.0
Also add DDR3A PHY reset before init for PG2.0 SoCs.
Acked-by: Murali Karicheri <m-maricheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/keystone/ddr3.c')
| -rw-r--r-- | arch/arm/cpu/armv7/keystone/ddr3.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c index bb16551eb2..b711b810cb 100644 --- a/arch/arm/cpu/armv7/keystone/ddr3.c +++ b/arch/arm/cpu/armv7/keystone/ddr3.c @@ -8,6 +8,7 @@ */ #include <asm/io.h> +#include <common.h> #include <asm/arch/ddr3.h> void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) @@ -67,3 +68,21 @@ void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET); __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET); } + +void ddr3_reset_ddrphy(void) +{ + u32 tmp; + + /* Assert DDR3A PHY reset */ + tmp = readl(K2HK_DDR3APLLCTL1); + tmp |= KS2_DDR3_PLLCTRL_PHY_RESET; + writel(tmp, K2HK_DDR3APLLCTL1); + + /* wait 10us to catch the reset */ + udelay(10); + + /* Release DDR3A PHY reset */ + tmp = readl(K2HK_DDR3APLLCTL1); + tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET; + __raw_writel(tmp, K2HK_DDR3APLLCTL1); +} |
