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| author | Alim Akhtar <alim.akhtar@samsung.com> | 2014-11-13 22:38:18 +0530 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2014-11-17 19:03:38 +0900 |
| commit | 061091098a5ec55ff4b68b61592af8619c2c7d88 (patch) | |
| tree | b5339bc118f1e114d79713dc0e6bf5022e025085 /arch/arm/cpu/armv7/exynos | |
| parent | 79043d84da076e4eb47e04495c55216897c9a161 (diff) | |
| download | blackbird-obmc-uboot-061091098a5ec55ff4b68b61592af8619c2c7d88.tar.gz blackbird-obmc-uboot-061091098a5ec55ff4b68b61592af8619c2c7d88.zip | |
DMC: Exynos5: Enable update mode for DREX controller
As per Exynos5800 UM ver 0.00 section 17.13.2.1
CONCONTROL register bit 3 [update_mode], Exynos5800 does not
support the PHY initiated update. And it is recommanded to
set this field to 1'b1 during initialization. This patch sets this bit.
Applying MC-initiated mode makes DDL tracking ON, that helps in
compensate MIF voltage variation.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/cpu/armv7/exynos')
| -rw-r--r-- | arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index b86dd2d650..4d73b45435 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -832,6 +832,25 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG); setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG); + /* + * As per Exynos5800 UM ver 0.00 section 17.13.2.1 + * CONCONTROL register bit 3 [update_mode], Exynos5800 does not + * support the PHY initiated update. And it is recommended to set + * this field to 1'b1 during initialization + * + * When we apply PHY-initiated mode, DLL lock value is determined + * once at DMC init time and not updated later when we change the MIF + * voltage based on ASV group in kernel. Applying MC-initiated mode + * makes sure that DLL tracing is ON so that silicon is able to + * compensate the voltage variation. + */ + val = readl(&drex0->concontrol); + val |= CONCONTROL_UPDATE_MODE; + writel(val , &drex0->concontrol); + val = readl(&drex1->concontrol); + val |= CONCONTROL_UPDATE_MODE; + writel(val , &drex1->concontrol); + return 0; } #endif |
