diff options
| author | Akshay Saraswat <akshay.s@samsung.com> | 2014-05-26 19:20:08 +0530 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2014-06-13 17:05:14 +0900 |
| commit | ed32522fe048f9edcb3269c8d5af79c6e8c6daea (patch) | |
| tree | 61a005141819f84aa56f8588f87cc78f575f42d6 /arch/arm/cpu/armv7/exynos/exynos5_setup.h | |
| parent | c9334fcda90652e2f8c49f4517b728ebc6f5f623 (diff) | |
| download | blackbird-obmc-uboot-ed32522fe048f9edcb3269c8d5af79c6e8c6daea.tar.gz blackbird-obmc-uboot-ed32522fe048f9edcb3269c8d5af79c6e8c6daea.zip | |
Exynos5420: DMC: Add software read leveling
Sometimes Read DQ and DQS are not in phase. Since, this
phase shift differs from board to board, we need to
calibrate it at DRAM init phase, that's read DQ calibration.
This patch adds SW Read DQ calibration routine to compensate
this skew.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/cpu/armv7/exynos/exynos5_setup.h')
| -rw-r--r-- | arch/arm/cpu/armv7/exynos/exynos5_setup.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index d415c91f3a..d91e585ea6 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -282,8 +282,11 @@ #define PHY_CON12_VAL 0x10107F50 #define CTRL_START (1 << 6) #define CTRL_DLL_ON (1 << 5) +#define CTRL_LOCK_COARSE_OFFSET 10 +#define CTRL_LOCK_COARSE_MASK (0x7F << CTRL_LOCK_COARSE_OFFSET) +#define CTRL_LOCK_COARSE(x) (((x) & CTRL_LOCK_COARSE_MASK) >> \ + CTRL_LOCK_COARSE_OFFSET) #define CTRL_FORCE_MASK (0x7F << 8) -#define CTRL_LOCK_COARSE_MASK (0x7F << 10) #define CTRL_FINE_LOCKED 0x7 #define CTRL_OFFSETD_RESET_VAL 0x8 |
