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| author | Tom Rini <trini@ti.com> | 2014-01-10 10:56:00 -0500 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-01-10 10:56:00 -0500 |
| commit | 7f673c99c2d8d1aa21996c5b914f06d784b080ca (patch) | |
| tree | df68108a0bd7326dc6299b96853b769220c55470 /arch/arm/cpu/armv7/exynos/clock_init.h | |
| parent | 8401bfa91ef57e331e2a3abdf768d41803bec88e (diff) | |
| parent | 10a147bc665367111920be657409a5d56d3c0590 (diff) | |
| download | blackbird-obmc-uboot-7f673c99c2d8d1aa21996c5b914f06d784b080ca.tar.gz blackbird-obmc-uboot-7f673c99c2d8d1aa21996c5b914f06d784b080ca.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be
added to include/configs/exynos5-dt.h now.
Conflicts:
include/configs/exynos5250-dt.h
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/exynos/clock_init.h')
| -rw-r--r-- | arch/arm/cpu/armv7/exynos/clock_init.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h b/arch/arm/cpu/armv7/exynos/clock_init.h index c28ff3ab14..a875d0b48f 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init.h +++ b/arch/arm/cpu/armv7/exynos/clock_init.h @@ -10,7 +10,11 @@ #define __EXYNOS_CLOCK_INIT_H enum { +#ifdef CONFIG_EXYNOS5420 + MEM_TIMINGS_MSR_COUNT = 5, +#else MEM_TIMINGS_MSR_COUNT = 4, +#endif }; /* These are the ratio's for configuring ARM clock */ @@ -59,6 +63,18 @@ struct mem_timings { unsigned bpll_mdiv; unsigned bpll_pdiv; unsigned bpll_sdiv; + unsigned kpll_mdiv; + unsigned kpll_pdiv; + unsigned kpll_sdiv; + unsigned dpll_mdiv; + unsigned dpll_pdiv; + unsigned dpll_sdiv; + unsigned ipll_mdiv; + unsigned ipll_pdiv; + unsigned ipll_sdiv; + unsigned spll_mdiv; + unsigned spll_pdiv; + unsigned spll_sdiv; unsigned pclk_cdrex_ratio; unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; @@ -115,6 +131,7 @@ struct mem_timings { uint8_t send_zq_init; /* 1 to send this command */ unsigned impedance; /* drive strength impedeance */ uint8_t gate_leveling_enable; /* check gate leveling is enabled */ + uint8_t read_leveling_enable; /* check h/w read leveling is enabled */ }; /** |
