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authorMichal Simek <michal.simek@xilinx.com>2013-05-08 15:37:28 +0200
committerMichal Simek <michal.simek@xilinx.com>2013-08-12 08:59:55 +0200
commit39523bef29f71967247ca00fe4b2c7e0831bb8a2 (patch)
tree13eb99a9c67cb1a21cadfb5089249310be548abd /arch/arm/cpu/armv7/am33xx/Makefile
parent148ba55cc618eaca19d7c86bdc003a7a71ee3a92 (diff)
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zynq: slcr: Wait 100ms till clk is properly setup
If you don't wait you will loose the first sent packet even all bits in emacps are correctly setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
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