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| author | Albert ARIBAUD \(3ADEV\) <albert.aribaud@3adev.fr> | 2015-03-31 11:40:47 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-04-10 14:23:20 +0200 |
| commit | 981219eebe3cc29f155a37951788c18786260514 (patch) | |
| tree | 00085f2e4a1f7834674720f636a6a82a06e3d897 /arch/arm/cpu/arm926ejs | |
| parent | 606f7047603422746d112e41937649d44f311af4 (diff) | |
| download | blackbird-obmc-uboot-981219eebe3cc29f155a37951788c18786260514.tar.gz blackbird-obmc-uboot-981219eebe3cc29f155a37951788c18786260514.zip | |
lpc32xx: add LPC32xx SSP support (SPI mode)
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Diffstat (limited to 'arch/arm/cpu/arm926ejs')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index a407098eda..5a453e303d 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -8,11 +8,13 @@ #include <asm/arch/cpu.h> #include <asm/arch/clk.h> #include <asm/arch/uart.h> +#include <asm/arch/mux.h> #include <asm/io.h> #include <dm.h> static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE; +static struct mux_regs *mux = (struct mux_regs *)MUX_BASE; void lpc32xx_uart_init(unsigned int uart_id) { @@ -66,3 +68,15 @@ void lpc32xx_i2c_init(unsigned int devnum) U_BOOT_DEVICE(lpc32xx_gpios) = { .name = "gpio_lpc32xx" }; + +/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */ + +#define P_MUX_SET_SSP0 0x1600 + +void lpc32xx_ssp_init(void) +{ + /* Enable SSP0 interface */ + writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl); + /* Mux SSP0 pins */ + writel(P_MUX_SET_SSP0, &mux->p_mux_set); +} |
