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| author | Otavio Salvador <otavio@ossystems.com.br> | 2012-08-05 09:05:31 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:17 +0200 |
| commit | 9c471142bc6c5aa01532ba85ead8509bbf2eb153 (patch) | |
| tree | 31f9e67e6c63a7abf63997bb9542fbd3075a61da /arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | |
| parent | ddcf13b15231ee2dca99285349b143c365ce5173 (diff) | |
| download | blackbird-obmc-uboot-9c471142bc6c5aa01532ba85ead8509bbf2eb153.tar.gz blackbird-obmc-uboot-9c471142bc6c5aa01532ba85ead8509bbf2eb153.zip | |
mxs: prefix register structs with 'mxs' prefix
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Diffstat (limited to 'arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index cca131688b..e7ed5e091c 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -100,8 +100,8 @@ void init_mx28_200mhz_ddr2(void) void mx28_mem_init_clock(void) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; /* Gate EMI clock */ writeb(CLKCTRL_FRAC_CLKGATE, @@ -131,8 +131,8 @@ void mx28_mem_init_clock(void) void mx28_mem_setup_cpu_and_hbus(void) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz * and ungate CPU clock */ @@ -163,8 +163,8 @@ void mx28_mem_setup_cpu_and_hbus(void) void mx28_mem_setup_vdda(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; writel((0xc << POWER_VDDACTRL_TRG_OFFSET) | (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) | @@ -174,8 +174,8 @@ void mx28_mem_setup_vdda(void) void mx28_mem_setup_vddd(void) { - struct mx28_power_regs *power_regs = - (struct mx28_power_regs *)MXS_POWER_BASE; + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) | (0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) | @@ -204,10 +204,10 @@ uint32_t mx28_mem_get_size(void) void mx28_mem_init(void) { - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - struct mx28_pinctrl_regs *pinctrl_regs = - (struct mx28_pinctrl_regs *)MXS_PINCTRL_BASE; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mxs_pinctrl_regs *pinctrl_regs = + (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE; /* Set DDR2 mode */ writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, |
